addis
Add Immediate Shifted - 3C 00 00 00
addis
Instruction Syntax
| Mnemonic | Format | Description |
| addis | rD,rA,SIMM | Add immediate shifted |
Derived Forms
| Mnemonic | Format | Description |
| lis | rD,value | Load immediate shifted (rA = 0) |
| subis | rD,rA,value | Subtract immediate shifted (SIMM = -value) |
Instruction Encoding
0
0
1
1
1
1
D
D
D
D
D
A
A
A
A
A
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
| Field | Bits | Description |
| Primary Opcode | 0-5 | 001111 (0x0F) |
| rD | 6-10 | Destination register |
| rA | 11-15 | Source register A (0 for lis) |
| SIMM | 16-31 | 16-bit signed immediate value |
Operation
if rA = 0 then rD ← EXTS(SIMM || 0x0000) else rD ← (rA) + EXTS(SIMM || 0x0000)
If rA is 0, the immediate value is shifted left 16 bits (concatenated with 16 zero bits) and placed into rD. Otherwise, the sum of the contents of rA and the shifted immediate value is placed into rD.
Note: The addis instruction does not update the carry bit (XER[CA]) and has no overflow exception option.
Affected Registers
None - This instruction does not affect any condition register fields or XER register bits.
Examples
Basic Immediate Shifted Addition
addis r3, r1, 0x1000 # r3 = r1 + 0x10000000 addis r5, r5, -1 # r5 = r5 + 0xFFFF0000 (subtract high)
Load Immediate Shifted (lis)
lis r3, 0x8000 # r3 = 0x80000000 (load high word) lis r4, 0x1234 # r4 = 0x12340000
Load 32-bit Constants
# Load full 32-bit constant 0x12345678 lis r3, 0x1234 # r3 = 0x12340000 ori r3, r3, 0x5678 # r3 = 0x12345678 # Alternative negative constant lis r4, -1 # r4 = 0xFFFF0000 ori r4, r4, 0xFFFF # r4 = 0xFFFFFFFF
Address Calculation
# Calculate address in high memory lis r5, 0x8000 # Load base address 0x80000000 lwz r6, 0x100(r5) # Load from 0x80000100
Subtract Immediate Shifted (subis)
subis r3, r1, 0x10 # r3 = r1 - 0x00100000