Instruction Syntax

Mnemonic	Format	Flags
stwux	rS,rA,rB	None

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rS	6-10	Source register
rA	11-15	Base register (updated)
rB	16-20	Index register
Reserved	21-29	000000000
Reserved	30-31	00

Operation

EA ← (rA) + (rB)
(EA) ← (rS)
rA ← EA

The effective address is calculated by adding the base register to the index register. The word (32-bit value) in the source register is stored at the effective address. The base register is updated with the effective address.

Note: The stwux instruction stores a 32-bit word to memory and updates the base register with the effective address. The address must be aligned to a 4-byte boundary.

Affected Registers

General Purpose Registers (GPRs)

• rA (Base register) - Updated with effective address

Memory

• Word at effective address (EA)

Examples

Basic Store Word with Update Indexed

# Store word using indexed addressing with update
stwux r1, r3, r4    # Store r1 at r3 + r4, then r3 = r3 + r4

Array of Words with Dynamic Index

# Store words in array using dynamic index
li r3, array         # Load array base address
li r4, 0             # Index = 0
stwux r1, r3, r4     # Store word, update base address

Data Processing with Dynamic Addressing

# Process data with dynamic addressing
li r3, data_buffer   # Load data buffer address
li r4, 0             # Index = 0
process_loop:
add r5, r6, r7       # Calculate value
stwux r5, r3, r4     # Store word, update base address
addi r4, r4, 4       # Increment index by 4 bytes
cmpwi r4, 400        # Check if done (100 words * 4 bytes)
blt process_loop

Related Instructions

stw, stwu, stwx, lwux