Register Reference
The PowerPC Gekko microprocessor programming model consists of three nested levels:
- USER MODEL UISA (User Instruction Set Architecture) - Basic user-accessible registers
- USER MODEL VEA (Virtual Environment Architecture) - Virtual memory and extended user registers
- SUPERVISOR MODEL OEA (Operating Environment Architecture) - System control and supervisor registers
User Model UISA
The User Instruction Set Architecture (UISA) provides the basic instruction set and registers accessible to user programs. These registers are available in both user and supervisor modes.
General Purpose Registers (GPRs)
32 general-purpose registers (r0-r31), each 32 bits wide. These are the primary registers for data storage, computation, and addressing.
| Register | Name | Description |
| r0-r31 | General Purpose Registers | 32-bit registers for data storage and computation. Used for variables, addresses, and intermediate calculations. |
| r1 | Stack Pointer | Conventionally used as stack pointer. Points to the current stack frame for function calls and local variables. |
| r2 | TOC Pointer | Conventionally used as TOC (Table of Contents) pointer. Contains the base address for accessing global variables and constants. |
| r3-r10 | Parameter Registers | Used for function parameters and return values. r3-r4 are also used for return values from functions. |
Condition Register (CR)
32-bit register divided into 8 fields (CR0-CR7), each containing 4 condition bits. Used to store the results of comparison and arithmetic operations for conditional branching.
Condition Register Layout
| Field | Bits | Condition Bits |
| CR7 | 28-31 | LT GT EQ SO |
| CR6 | 24-27 | LT GT EQ SO |
| CR5 | 20-23 | LT GT EQ SO |
| CR4 | 16-19 | LT GT EQ SO |
| CR3 | 12-15 | LT GT EQ SO |
| CR2 | 8-11 | LT GT EQ SO |
| CR1 | 4-7 | LT GT EQ SO |
| CR0 | 0-3 | LT GT EQ SO |
Condition Register Fields
| Field | Name | Description |
| LT | Less Than | Set when result is negative (bit 0 of each CR field). Used for signed comparisons. |
| GT | Greater Than | Set when result is positive and non-zero (bit 1 of each CR field). Used for signed comparisons. |
| EQ | Equal | Set when result is zero (bit 2 of each CR field). Used for equality comparisons. |
| SO | Summary Overflow | Set when overflow occurs or XER[SO] is set (bit 3 of each CR field). Sticky overflow indicator. |
Exception Register (XER)
32-bit register containing overflow and carry information from arithmetic operations. Used to detect and handle arithmetic exceptions.
Exception Register Layout
| Field | Bits | Description |
| Reserved | 0-25 | Reserved bits for future use |
| SO | 26 | Summary Overflow - Sticky overflow flag |
| OV | 27 | Overflow - Overflow flag for the most recent operation |
| CA | 28 | Carry - Carry flag from arithmetic operations |
| Reserved | 29-31 | Reserved bits for future use |
XER Fields
| Field | Name | Description |
| SO | Summary Overflow | Sticky overflow flag, set when any overflow occurs and remains set until explicitly cleared. Used for detecting arithmetic overflow conditions. |
| OV | Overflow | Overflow flag for the most recent operation. Indicates if the last arithmetic operation resulted in overflow. |
| CA | Carry | Carry flag from arithmetic operations. Set when an addition produces a carry or subtraction requires a borrow. |
Link Register (LR)
| SPR | Register | Description |
| 8 | LR | Link Register - 32-bit register storing return address for subroutine calls. Automatically set by branch-and-link instructions (bl, bla) to enable function returns. |
Count Register (CTR)
| SPR | Register | Description |
| 9 | CTR | Count Register - 32-bit register used for loop counting and indirect branches. Can be decremented and tested for zero, making it ideal for loop control and computed branches. |
Floating-Point Registers (FPRs)
32 floating-point registers (f0-f31), each 64 bits wide. Used for floating-point arithmetic operations and can store both single and double precision values.
| Register | Name | Description |
| f0-f31 | Floating-Point Registers | 64-bit registers for floating-point operations. Can store IEEE 754 single or double precision floating-point values. |
| f1 | Floating-Point Parameter 1 | First floating-point parameter and return value. Used for passing floating-point arguments to functions. |
| f2-f8 | Floating-Point Parameters | Additional floating-point parameters. Used for passing multiple floating-point arguments to functions. |
Floating-Point Status and Control Register (FPSCR)
32-bit register containing floating-point status and control bits. Controls floating-point exception handling, rounding modes, and stores status information from floating-point operations.
FPSCR Layout
| Field | Bits | Description |
| FX | 0 | Floating-point exception summary - Set when any floating-point exception occurs |
| FEX | 1 | Floating-point enabled exception summary - Set when any enabled exception occurs |
| VX | 2 | Floating-point invalid operation exception - Set for invalid operations like 0/0 |
| OX | 3 | Floating-point overflow exception - Set when result exceeds representable range |
| UX | 4 | Floating-point underflow exception - Set when result is too small to represent |
| ZX | 5 | Floating-point zero divide exception - Set when dividing by zero |
| XX | 6 | Floating-point inexact exception - Set when result cannot be exactly represented |
| VXSNAN | 7 | Floating-point invalid operation (SNaN) - Set when operating on signaling NaN |
| VXISI | 8 | Floating-point invalid operation (infinity - infinity) - Set for invalid infinity operations |
| VXIDI | 9 | Floating-point invalid operation (infinity / infinity) - Set for invalid infinity division |
| VXZDZ | 10 | Floating-point invalid operation (0 / 0) - Set for zero divided by zero |
| VXIMZ | 11 | Floating-point invalid operation (infinity * 0) - Set for infinity times zero |
| VXVC | 12 | Floating-point invalid operation (invalid compare) - Set for invalid comparisons |
| FR | 13 | Floating-point fraction rounded - Set when fraction was rounded |
| FI | 14 | Floating-point fraction inexact - Set when fraction cannot be exactly represented |
| FPRF | 15-19 | Floating-point result flags - Indicates result type (normal, zero, infinity, NaN) |
| Reserved | 20-23 | Reserved bits for future use |
| VE | 24 | Floating-point invalid operation exception enable - Controls whether invalid operations generate exceptions |
| OE | 25 | Floating-point overflow exception enable - Controls whether overflow generates exceptions |
| UE | 26 | Floating-point underflow exception enable - Controls whether underflow generates exceptions |
| ZE | 27 | Floating-point zero divide exception enable - Controls whether zero divide generates exceptions |
| XE | 28 | Floating-point inexact exception enable - Controls whether inexact results generate exceptions |
| NI | 29 | Floating-point non-IEEE mode - When set, disables IEEE 754 compliance |
| RN | 30-31 | Floating-point rounding mode - Controls how inexact results are rounded |
Performance Monitor Registers (For Reading)
These registers allow user programs to monitor performance metrics without requiring supervisor privileges.
Performance Counters
| SPR | Register | Description |
| 937 | UPMC1 | User Performance Monitor Counter 1 - Counts user-accessible performance events like cache misses, branch mispredictions, or instruction completions |
| 938 | UPMC2 | User Performance Monitor Counter 2 - Second user-accessible performance counter for different event types |
| 941 | UPMC3 | User Performance Monitor Counter 3 - Third user-accessible performance counter |
| 942 | UPMC4 | User Performance Monitor Counter 4 - Fourth user-accessible performance counter |
User Monitor Control
| SPR | Register | Description |
| 936 | UMMCR0 | User Monitor Mode Control Register 0 - Controls which events are counted by user performance counters and sampling modes |
| 940 | UMMCR1 | User Monitor Mode Control Register 1 - Additional control bits for user performance monitoring configuration |
User Sampled Instruction Address
| SPR | Register | Description |
| 939 | USIA | User Sampled Instruction Address - Contains the address of the instruction that triggered a performance sampling event |
Special Purpose Registers (SPRs)
| SPR | Register | Description |
| 1 | XER | Exception Register - Contains overflow and carry flags from arithmetic operations |
| 8 | LR | Link Register - Return address for subroutine calls |
| 9 | CTR | Count Register - Loop counter and indirect branch target |
User Model VEA
The Virtual Environment Architecture (VEA) provides virtual memory support and additional user-accessible registers. These registers extend the basic UISA functionality with virtual memory capabilities and enhanced performance monitoring.
Time Base Facility (For Reading)
The Time Base provides a high-resolution timer that increments at a fixed frequency, useful for timing measurements and real-time applications.
| TBR | Register | Description |
| 268 | TBL | Time Base Lower (for reading) - Lower 32 bits of the 64-bit time base counter. Provides high-resolution timing for user applications. |
| 269 | TBU | Time Base Upper (for reading) - Upper 32 bits of the 64-bit time base counter. Used with TBL for extended timing periods. |
Quantization Registers
Graphics Quantization Registers (GQR) control the conversion between different data formats for graphics operations, particularly useful for GameCube graphics processing.
| SPR | Register | Description |
| 912 | GQR0 | Graphics Quantization Register 0 - Controls data format conversion for graphics operations, specifying source and destination formats |
| 913 | GQR1 | Graphics Quantization Register 1 - Second quantization control register for different graphics data types |
| 914 | GQR2 | Graphics Quantization Register 2 - Third quantization control register |
| 915 | GQR3 | Graphics Quantization Register 3 - Fourth quantization control register |
| 916 | GQR4 | Graphics Quantization Register 4 - Fifth quantization control register |
| 917 | GQR5 | Graphics Quantization Register 5 - Sixth quantization control register |
| 918 | GQR6 | Graphics Quantization Register 6 - Seventh quantization control register |
| 919 | GQR7 | Graphics Quantization Register 7 - Eighth quantization control register |
Performance Monitor Registers
Enhanced performance monitoring registers that provide more detailed system performance information than the UISA performance registers.
Performance Counters
| SPR | Register | Description |
| 953 | PMC1 | Performance Monitor Counter 1 - Counts system-wide performance events including cache operations, memory accesses, and pipeline stalls |
| 954 | PMC2 | Performance Monitor Counter 2 - Second system performance counter for different event categories |
| 957 | PMC3 | Performance Monitor Counter 3 - Third system performance counter |
| 958 | PMC4 | Performance Monitor Counter 4 - Fourth system performance counter |
Monitor Control
| SPR | Register | Description |
| 952 | MMCR0 | Monitor Mode Control Register 0 - Controls system-wide performance monitoring, including event selection, sampling modes, and interrupt generation |
| 958 | MMCR1 | Monitor Mode Control Register 1 - Additional control bits for system performance monitoring configuration and advanced features |
Sampled Instruction Address
| SPR | Register | Description |
| 955 | SIA | Sampled Instruction Address - Contains the address of the instruction that triggered a system-wide performance sampling event |
Supervisor Model OEA
The Operating Environment Architecture (OEA) provides the highest level of system control and includes all registers accessible only in supervisor mode. These registers control memory management, exception handling, and system configuration.
Hardware Implementation Registers
These registers control hardware-specific features and provide information about the processor implementation.
| SPR | Register | Description |
| 1008 | HID0 | Hardware Implementation Register 0 - Controls processor-specific features like instruction cache, data cache, and branch prediction settings |
| 1009 | HID1 | Hardware Implementation Register 1 - Additional processor-specific control bits for advanced features and optimizations |
| 920 | HID2 | Hardware Implementation Register 2 - Controls GameCube-specific features like the graphics interface and memory controller settings |
| 269 | TBR | Time Base Register - Contains the current value of the time base counter for system timing and synchronization |
Configuration Registers
These registers provide information about the processor and control the overall machine state.
| SPR | Register | Description |
| 287 | PVR | Processor Version Register - Contains the processor version and revision information, used to identify the specific PowerPC implementation |
| - | MSR | Machine State Register - Controls the overall processor state including privilege level, interrupt enables, and execution modes |
Machine State Register (MSR)
The Machine State Register (MSR) is a 32-bit register that controls the overall processor state and execution environment. It determines privilege level, interrupt handling, and various execution modes.
MSR Bit Layout
| Bit | Name | Description |
| 0 | POW | Power Management - When set, processor can enter power management mode |
| 1 | ILE | Interrupt Little Endian - When set, interrupts are handled in little-endian mode |
| 2 | EE | External Interrupt Enable - When set, external interrupts are enabled |
| 3 | PR | Privilege Level - When set, processor runs in user mode; when clear, in supervisor mode |
| 4 | FP | Floating-Point Available - When set, floating-point instructions are available |
| 5 | ME | Machine Check Enable - When set, machine check interrupts are enabled |
| 6 | FE0 | Floating-Point Exception Mode 0 - Controls floating-point exception handling |
| 7 | SE | Single Step Enable - When set, single-step debugging is enabled |
| 8 | BE | Branch Trace Enable - When set, branch tracing is enabled |
| 9 | FE1 | Floating-Point Exception Mode 1 - Additional floating-point exception control |
| 10 | IP | Exception Prefix - When set, exceptions use prefix 0xFFF00000; when clear, use 0x00000000 |
| 11 | IR | Instruction Relocate - When set, instruction address translation is enabled |
| 12 | DR | Data Relocate - When set, data address translation is enabled |
| 13-15 | Reserved | Reserved bits for future use |
| 16-31 | Reserved | Reserved bits for future use |
MSR Usage Examples
Reading MSR: Use mfmsr rD to copy MSR contents to a general-purpose register.
Writing MSR: Use mtmsr rS to copy a general-purpose register to MSR (supervisor mode only).
Privilege Level Control: The PR bit (bit 3) controls whether the processor runs in user mode (PR=1) or supervisor mode (PR=0).
Interrupt Control: The EE bit (bit 2) enables/disables external interrupts, while ME bit (bit 5) controls machine check interrupts.
Address Translation: IR bit (bit 11) enables instruction address translation, DR bit (bit 12) enables data address translation.
Memory Management Registers
These registers control the memory management unit (MMU) and virtual memory translation.
Instruction BAT Registers
Block Address Translation (BAT) registers provide fast virtual-to-physical address translation for instruction memory. BATs are faster than page tables but can only map large, aligned memory blocks. Each BAT consists of an Upper (U) and Lower (L) register pair.
BAT Register Format
BAT Upper Register (IBATxU): Contains virtual address, protection bits, and block size
BAT Lower Register (IBATxL): Contains physical address and additional control bits
| SPR | Register | Description |
| 528 | IBAT0U | Instruction BAT 0 Upper - Contains virtual address bits 0-14, protection bits (PP), and block size (BL) |
| 529 | IBAT0L | Instruction BAT 0 Lower - Contains physical address bits 0-14 and additional control bits |
| 530 | IBAT1U | Instruction BAT 1 Upper - Second instruction BAT for additional memory mapping |
| 531 | IBAT1L | Instruction BAT 1 Lower - Physical address and control for second instruction BAT |
| 532 | IBAT2U | Instruction BAT 2 Upper - Third instruction BAT for extended memory mapping |
| 533 | IBAT2L | Instruction BAT 2 Lower - Physical address and control for third instruction BAT |
| 534 | IBAT3U | Instruction BAT 3 Upper - Fourth instruction BAT for maximum memory mapping |
| 535 | IBAT3L | Instruction BAT 3 Lower - Physical address and control for fourth instruction BAT |
BAT Protection Bits (PP)
| Value | Protection | Description |
| 00 | No Access | No access allowed, generates protection violation |
| 01 | Read-Only | Read access allowed, write generates protection violation |
| 10 | Read-Write | Both read and write access allowed |
| 11 | Read-Write | Both read and write access allowed (same as 10) |
BAT Block Sizes (BL)
| Value | Block Size | Description |
| 00000 | 128 KB | Smallest BAT block size |
| 00001 | 256 KB | 256 kilobyte blocks |
| 00010 | 512 KB | 512 kilobyte blocks |
| 00011 | 1 MB | 1 megabyte blocks |
| 00100 | 2 MB | 2 megabyte blocks |
| 00101 | 4 MB | 4 megabyte blocks |
| 00110 | 8 MB | 8 megabyte blocks |
| 00111 | 16 MB | 16 megabyte blocks |
| 01000 | 32 MB | 32 megabyte blocks |
| 01001 | 64 MB | 64 megabyte blocks |
| 01010 | 128 MB | 128 megabyte blocks |
| 01011 | 256 MB | 256 megabyte blocks |
Data BAT Registers
Data BAT registers provide fast virtual-to-physical address translation for data memory, similar to instruction BATs but for data accesses. They use the same format and protection scheme as instruction BATs.
| SPR | Register | Description |
| 536 | DBAT0U | Data BAT 0 Upper - Virtual address, protection bits, and block size for data memory |
| 537 | DBAT0L | Data BAT 0 Lower - Physical address and control bits for data memory |
| 538 | DBAT1U | Data BAT 1 Upper - Second data BAT for additional data memory mapping |
| 539 | DBAT1L | Data BAT 1 Lower - Physical address and control for second data BAT |
| 540 | DBAT2U | Data BAT 2 Upper - Third data BAT for extended data memory mapping |
| 541 | DBAT2L | Data BAT 2 Lower - Physical address and control for third data BAT |
| 542 | DBAT3U | Data BAT 3 Upper - Fourth data BAT for maximum data memory mapping |
| 543 | DBAT3L | Data BAT 3 Lower - Physical address and control for fourth data BAT |
BAT Usage Examples
Setting up a BAT for ROM mapping:
# Map 1MB of ROM at virtual address 0xFFF00000 to physical 0x00000000 # IBAT0U: Virtual address 0xFFF00000, protection 01 (read-only), block size 1MB lis r3, 0xFFF0 ori r3, r3, 0x0001 # Virtual address + protection + block size mtspr 528, r3 # Write to IBAT0U # IBAT0L: Physical address 0x00000000 lis r4, 0x0000 ori r4, r4, 0x0000 # Physical address mtspr 529, r4 # Write to IBAT0L
Setting up a BAT for RAM mapping:
# Map 8MB of RAM at virtual address 0x80000000 to physical 0x00000000 # DBAT0U: Virtual address 0x80000000, protection 10 (read-write), block size 8MB lis r3, 0x8000 ori r3, r3, 0x0006 # Virtual address + protection + block size mtspr 536, r3 # Write to DBAT0U # DBAT0L: Physical address 0x00000000 lis r4, 0x0000 ori r4, r4, 0x0000 # Physical address mtspr 537, r4 # Write to DBAT0L
Segment Registers
Segment registers provide additional address translation capabilities and memory protection for different address spaces. They work in conjunction with the BAT registers and page tables to provide flexible memory management.
Segment Register Format
Each segment register (SR0-SR15) contains a 32-bit segment identifier that is used in address translation. The segment identifier includes protection bits and a segment number.
| Register | Description |
| SR0-SR15 | Segment Registers 0-15 - Provide segment-based address translation and protection for different memory regions. Each segment can have different protection attributes and can map to different page table spaces. |
| SDR1 (SPR 25) | Storage Description Register 1 - Contains the base address of the page table for hash-based address translation. This register points to the root of the page table structure used when BAT translation fails. |
Segment Register Bit Layout
| Bits | Field | Description |
| 0-3 | Protection | Protection bits (PP) - Same encoding as BAT protection bits |
| 4-7 | Segment Number | Segment number used in address translation |
| 8-31 | Reserved | Reserved bits for future use |
Segment Register Usage
Setting a Segment Register:
# Set SR0 for read-write access to segment 1 li r3, 0x00000010 # Protection 10 (read-write) + segment 1 mtsr 0, r3 # Set SR0
Setting SDR1 for page table:
# Set SDR1 to point to page table at physical address 0x10000000 lis r3, 0x1000 # High 16 bits of page table address ori r3, r3, 0x0000 # Low 16 bits of page table address mtspr 25, r3 # Set SDR1
Exception Handling Registers
These registers are used by the exception handling mechanism to save processor state and provide information about exceptions.
SPRGx (Special Purpose Registers General)
SPRG registers provide temporary storage for critical processor state during exception handling, preventing corruption of user registers. They are used by the exception handling mechanism to save and restore processor state.
| SPR | Register | Description |
| 272 | SPRG0 | Special Purpose Register General 0 - Temporary storage for critical data during exception processing. Often used to save the exception vector number. |
| 273 | SPRG1 | Special Purpose Register General 1 - Additional temporary storage for exception handling. May be used to save processor state information. |
| 274 | SPRG2 | Special Purpose Register General 2 - Temporary storage for processor state during interrupts. Often used to save the current MSR value. |
| 275 | SPRG3 | Special Purpose Register General 3 - Additional temporary storage for critical exception data. May be used for interrupt-specific information. |
SPRG Usage in Exception Handlers
Exception Handler Entry:
# Save critical registers in SPRG mtsprg 0, r3 # Save r3 in SPRG0 mtsprg 1, r4 # Save r4 in SPRG1 mtsprg 2, r5 # Save r5 in SPRG2 mtsprg 3, r6 # Save r6 in SPRG3 # ... handle exception ... # Restore registers from SPRG mfsprg r3, 0 # Restore r3 from SPRG0 mfsprg r4, 1 # Restore r4 from SPRG1 mfsprg r5, 2 # Restore r5 from SPRG2 mfsprg r6, 3 # Restore r6 from SPRG3
Interrupt Registers
These registers store information about interrupts and exceptions for proper handling and recovery.
| SPR | Register | Description |
| 19 | DAR | Data Address Register - Contains the effective address that caused a data storage interrupt (page fault, protection violation, etc.). Used by the exception handler to determine which address caused the fault. |
| 18 | DSISR | Data Storage Interrupt Status Register - Contains status information about data storage interrupts including the type of fault and access details. Provides detailed information about why a data access failed. |
| 26 | SRR0 | Save/Restore Register 0 - Saves the instruction address where execution should resume after handling an exception. Contains the address of the instruction that caused the exception or where to return after handling it. |
| 27 | SRR1 | Save/Restore Register 1 - Saves the Machine State Register (MSR) contents at the time of the exception for proper restoration. Ensures that the processor state is correctly restored when returning from an exception. |
DSISR Bit Layout
| Bit | Name | Description |
| 0 | DSISR0 | Data storage interrupt status bit 0 |
| 1 | DSISR1 | Data storage interrupt status bit 1 |
| 2 | DSISR2 | Data storage interrupt status bit 2 |
| 3 | DSISR3 | Data storage interrupt status bit 3 |
| 4 | DSISR4 | Data storage interrupt status bit 4 |
| 5 | DSISR5 | Data storage interrupt status bit 5 |
| 6 | DSISR6 | Data storage interrupt status bit 6 |
| 7 | DSISR7 | Data storage interrupt status bit 7 |
| 8 | DSISR8 | Data storage interrupt status bit 8 |
| 9 | DSISR9 | Data storage interrupt status bit 9 |
| 10 | DSISR10 | Data storage interrupt status bit 10 |
| 11 | DSISR11 | Data storage interrupt status bit 11 |
| 12 | DSISR12 | Data storage interrupt status bit 12 |
| 13 | DSISR13 | Data storage interrupt status bit 13 |
| 14 | DSISR14 | Data storage interrupt status bit 14 |
| 15 | DSISR15 | Data storage interrupt status bit 15 |
| 16 | DSISR16 | Data storage interrupt status bit 16 |
| 17 | DSISR17 | Data storage interrupt status bit 17 |
| 18 | DSISR18 | Data storage interrupt status bit 18 |
| 19 | DSISR19 | Data storage interrupt status bit 19 |
| 20 | DSISR20 | Data storage interrupt status bit 20 |
| 21 | DSISR21 | Data storage interrupt status bit 21 |
| 22 | DSISR22 | Data storage interrupt status bit 22 |
| 23 | DSISR23 | Data storage interrupt status bit 23 |
| 24 | DSISR24 | Data storage interrupt status bit 24 |
| 25 | DSISR25 | Data storage interrupt status bit 25 |
| 26 | DSISR26 | Data storage interrupt status bit 26 |
| 27 | DSISR27 | Data storage interrupt status bit 27 |
| 28 | DSISR28 | Data storage interrupt status bit 28 |
| 29 | DSISR29 | Data storage interrupt status bit 29 |
| 30 | DSISR30 | Data storage interrupt status bit 30 |
| 31 | DSISR31 | Data storage interrupt status bit 31 |
Miscellaneous Registers
These registers provide various system control and debugging capabilities.
| SPR | Register | Description |
| 282 | EAR | External Access Register - Controls external bus access and provides status information about external memory operations |
| 284 | TBL | Time Base Lower (for writing) - Allows supervisor software to set the lower 32 bits of the time base counter |
| 285 | TBU | Time Base Upper (for writing) - Allows supervisor software to set the upper 32 bits of the time base counter |
| 22 | DEC | Decrementer - A decrementing counter that generates a decrementer interrupt when it reaches zero, used for timer functionality |
| 1013 | DABR | Data Address Breakpoint Register - Contains the address for data breakpoints, triggering an interrupt when the specified address is accessed |
| 1010 | IABR | Instruction Address Breakpoint Register - Contains the address for instruction breakpoints, triggering an interrupt when the specified instruction is executed |
| 921 | WPAR | Write Gather Pipe - Controls the write gather pipe for optimizing memory writes and cache operations |
| 1017 | L2CR | L2 Control Register - Controls the L2 cache configuration, including enable/disable, size, and replacement policy |
| 923 | DMAL | Direct Memory Access Lower - Lower portion of DMA control register for managing direct memory access operations |
| 922 | DMAU | Direct Memory Access Upper - Upper portion of DMA control register for managing direct memory access operations |
| 1023 | PIR | Processor ID Register - Contains a unique processor identifier used for multiprocessor systems to distinguish between different processors in the system |
Power/Thermal Management Registers
These registers control power management features and thermal monitoring to ensure proper processor operation.
| SPR | Register | Description |
| 1020 | THRM1 | Thermal Assist Unit Register 1 - Contains thermal monitoring data and control bits for the thermal assist unit |
| 1021 | THRM2 | Thermal Assist Unit Register 2 - Additional thermal monitoring and control information |
| 1022 | THRM3 | Thermal Assist Unit Register 3 - Extended thermal management control and status information |
| 1019 | ICTC | Instruction Cache Throttling Control Register - Controls instruction cache throttling to manage power consumption and thermal conditions |
Note: Registers marked with are processor-specific registers. They may not be supported by other PowerPC processors.