Instruction Syntax Conventions

Register Notation

Notation	Description	Details
rD	Destination Register	General Purpose Register (GPR) that receives the result
rA	Source Register A	First source operand register
rB	Source Register B	Second source operand register
rS	Source Register	Single source operand register

Instruction Flags and Modifiers

Flag	Name	Description
OE	Overflow Exception	Controls whether overflow exceptions are enabled (0=disabled, 1=enabled)
Rc	Record Condition Register	Controls whether condition register is updated (0=no update, 1=update CR0)
AA	Absolute Address	Branch target is absolute address (0=relative, 1=absolute)
LK	Link	Save return address in Link Register (0=no save, 1=save)

Special Registers

Register	Name	Description
CR	Condition Register	32-bit register with 8 fields (CR0-CR7), each containing 4 condition bits (LT, GT, EQ, SO)
XER	Exception Register	Contains overflow (OV), summary overflow (SO), and carry (CA) flags
LR	Link Register	Stores return address for subroutine calls
CTR	Count Register	Used for loop counting and indirect branches

Condition Register Fields

Field	Name	Description
LT	Less Than	Set when result is negative (bit 0 of CR field)
GT	Greater Than	Set when result is positive and non-zero (bit 1 of CR field)
EQ	Equal	Set when result is zero (bit 2 of CR field)
SO	Summary Overflow	Set when overflow occurs or XER[SO] is set (bit 3 of CR field)

Instruction Forms

Form	Name	Description
D	D-Form	Immediate instructions with 16-bit signed immediate value
DS	DS-Form	D-Form with shift (14-bit immediate, 2-bit shift)
I	I-Form	Branch instructions with 24-bit signed displacement
B	B-Form	Branch instructions with 14-bit signed displacement
X	X-Form	Register-register instructions (3 register operands)
XO	XO-Form	X-Form with OE and Rc bits

Addressing Modes

Mode	Name	Description
(rA)	Register Indirect	Address is contents of register rA
d(rA)	Base + Displacement	Address is (rA) + signed 16-bit displacement d
(rA)(rB)	Indexed	Address is (rA) + (rB)
d(rA)(rB)	Base + Index + Displacement	Address is (rA) + (rB) + signed displacement d

Common Mnemonics

Mnemonic	Name	Description
li	Load Immediate	Alias for addi rD,0,SIMM (load 16-bit signed immediate)
la	Load Address	Alias for addi rD,rA,SIMM (compute effective address)
subi	Subtract Immediate	Alias for addi rD,rA,-SIMM (subtract immediate)
lis	Load Immediate Shifted	Alias for addis rD,0,SIMM (load upper 16 bits)

Instruction Format Symbols

The following symbols are commonly used in PowerPC instruction documentation to describe operations, bit manipulations, and logical expressions:

Assignment and Assignment Operators

Symbol	Name	Description	Example
←	Assignment	Assigns the value on the right to the destination on the left	rD ← (rA) + (rB)
+	Addition	Arithmetic addition	rD ← (rA) + (rB)
-	Subtraction	Arithmetic subtraction	rD ← (rA) - (rB)
×	Multiplication	Arithmetic multiplication	rD ← (rA × rB)[32:63]
÷	Division	Arithmetic division	rD ← (rA) ÷ (rB)

Logical Operators

Symbol	Name	Description	Example
&	AND	Bitwise logical AND	rA ← (rS) & (rB)
|	OR	Bitwise logical OR	rA ← (rS) | (rB)
⊕	XOR	Bitwise exclusive OR	rA ← (rS) ⊕ (rB)
¬	NOT	Bitwise logical NOT (complement)	rA ← ¬(rS)
≡	Equivalence	Logical equivalence (XNOR)	rA ← (rS) ≡ (rB)

Shift and Rotate Operators

Symbol	Name	Description	Example
<<	Left Shift	Logical left shift	rA ← (rS) << (rB)[26:31]
>>	Right Shift	Logical right shift	rA ← (rS) >> (rB)[26:31]
ROTATE	Rotate	Circular rotation of bits	rA ← ROTATE((rS), SH)

Bit Range Notation

Symbol	Name	Description	Example
[n:m]	Bit Range	Extract bits n through m (inclusive)	(rS)[24:31]
[n]	Single Bit	Extract bit n	XER[CA]
||	Concatenation	Concatenate bit fields	0x0000 || temp

Comparison and Control Operators

Symbol	Name	Description	Example
=	Equal	Equality comparison	if rA = 0 then
≠	Not Equal	Inequality comparison	if CTR ≠ 0 then
<	Less Than	Less than comparison	if a < EXTS(SIMM) then
>	Greater Than	Greater than comparison	if a > EXTS(SIMM) then
≤	Less Than or Equal	Less than or equal comparison	if value ≤ limit then
≥	Greater Than or Equal	Greater than or equal comparison	if value ≥ threshold then

Special Functions and Operations

Symbol	Name	Description	Example
EXTS	Sign Extend	Sign extend a value	EA ← EXTS(d)
MEM	Memory Access	Memory read/write operation	rD ← MEM(EA, 4)
√	Square Root	Square root operation	frD ← √frB
SINGLE	Single Precision	Convert to single precision	frD ← SINGLE((frA × frC) + frB)
mod	Modulo	Modulo operation	(i mod 4)

Conditional and Control Flow

Symbol	Name	Description	Example
if...then	Conditional	Conditional execution	if rA = 0 then EA ← EXTS(d)
else	Else	Alternative execution path	else EA ← (rA) + EXTS(d)
←	Assignment	Assignment in conditional context	cond_ok ← BO[0] | (CR[BI] ≡ BO[1])

Register and Field Access

Symbol	Name	Description	Example
(rA)	Register Contents	Contents of register rA	EA ← (rA) + SIMM
CR[n]	Condition Register Bit	Access to condition register bit n	CR[crbD] ← CR[crbA] & CR[crbB]
XER[CA]	XER Field	Access to XER carry bit	rD ← (rA) + XER[CA]
FPSCR[n]	FPSCR Field	Access to floating-point status field	FPSCR[crfD] ← 1

Note: These symbols are used throughout the PowerPC instruction documentation to provide precise mathematical descriptions of instruction behavior. Understanding these symbols is essential for interpreting instruction specifications and understanding the exact operations performed by each instruction.

Branch Conditions

Condition	Name	Description
lt	Less Than	Branch if condition is less than (CR[LT] = 1)
gt	Greater Than	Branch if condition is greater than (CR[GT] = 1)
eq	Equal	Branch if condition is equal (CR[EQ] = 1)
so	Summary Overflow	Branch if summary overflow (CR[SO] = 1)
un	Unordered	Branch if unordered (floating-point comparison)