Instruction Syntax

Mnemonic	Format	Flags
andis.	rA,rS,UIMM	Rc = 1
andis	rA,rS,UIMM	Rc = 0

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011101 (0x1D)
rS	6-10	Source register
rA	11-15	Destination register
UIMM	16-31	Unsigned immediate value (16-bit)
Rc	31	Record Condition Register

Operation

rA ← (rS) & (ZEXT(UIMM) << 16)

ANDIS performs a bitwise AND operation between the source register and a zero-extended 16-bit unsigned immediate value shifted left by 16 positions.

1. Takes the value from source register rS
2. Zero-extends the 16-bit immediate value to 32 bits
3. Shifts the immediate value left by 16 positions
4. Performs bitwise AND operation
5. Stores the result in destination register rA

Note: ANDIS is used to mask the upper 16 bits of a register while preserving the lower 16 bits.

Affected Registers

General Purpose Registers (GPRs)

• rA (Destination register) - Result of AND operation

Condition Register (CR0 field)

(if Rc = 1)

• LT (Less Than)
• GT (Greater Than)
• EQ (Equal)
• SO (Summary Overflow)

Examples

Basic AND Shifted Operation

# Clear upper 16 bits of a register
andis r3, r4, 0x0000    # r3 = r4 & 0x00000000 (clear upper 16 bits)
andis. r3, r4, 0x0000   # Same as above, but also sets condition register

Upper Bit Masking

# Extract upper 8 bits (bits 24-31)
andis r3, r4, 0xFF00    # r3 = r4 & 0xFF000000

# Clear specific upper bits
andis r3, r4, 0x7FFF    # Clear bit 31: r3 = r4 & 0x7FFF0000
andis r3, r4, 0xBFFF    # Clear bit 30: r3 = r4 & 0xBFFF0000

Testing Upper Bit Patterns

# Test if upper 4 bits are set
andis r3, r4, 0xF000    # r3 = r4 & 0xF0000000 (bits 28-31)
cmpwi r3, 0xF0000000    # Compare with expected pattern
beq upper_bits_set      # Branch if all upper bits are set

Flag Checking in Upper Bits

# Check if a specific flag is set in upper bits
andis r3, r4, 0x8000    # Test bit 31 (sign flag)
cmpwi r3, 0             # Compare with zero
bne sign_flag_set       # Branch if sign flag is set

Register Clearing

# Clear upper 16 bits while preserving lower 16
andis r3, r3, 0x0000    # r3 = r3 & 0x00000000 (clear upper 16 bits)

# Set specific upper bits
andis r3, r3, 0xFFFF    # r3 = r3 & 0xFFFF0000 (keep upper 16 bits)

Data Validation

# Validate upper 16 bits are in range
andis r3, r4, 0x7FFF    # Ensure upper bits are positive
cmpw r3, r4             # Compare with original
bne invalid_upper_bits  # Branch if upper bits were negative

Related Instructions

and (AND), andi (AND Immediate), oris (OR Immediate Shifted), xoris (XOR Immediate Shifted)