and
AND - 7C 00 00 38
and
Instruction Syntax
Mnemonic | Format | Flags |
and | rA,rS,rB | Rc = 0 |
and. | rA,rS,rB | Rc = 1 |
Instruction Encoding
0
1
1
1
1
1
S
S
S
S
S
A
A
A
A
A
B
B
B
B
B
0
0
0
0
0
1
1
1
0
0
Rc
Field | Bits | Description |
Primary Opcode | 0-5 | 011111 (0x1F) |
rS | 6-10 | Source register S |
rA | 11-15 | Destination register A |
rB | 16-20 | Source register B |
Reserved | 21 | Should be zero |
XO | 22-29 | 28 (Extended opcode) |
Rc | 30-31 | Record Condition Register |
Operation
rA ← (rS) & (rB)
The bitwise AND of the contents of rS and rB is placed into rA.
Note: This instruction performs a bitwise logical AND operation on each bit position.
Affected Registers
Condition Register (CR0 field)
(if Rc = 1)
- LT (Less Than)
- GT (Greater Than)
- EQ (Equal)
- SO (Summary Overflow)
For more information on condition codes see Section 2.1.3, "Condition Register," in the PowerPC Microprocessor Family: The Programming Environments manual.
Examples
Basic Logical AND
and r3, r1, r2 # r3 = r1 & r2 and. r3, r1, r2 # Same as above, but also sets condition register
Bit Masking
# Clear specific bits using mask li r4, 0x00FF # Load mask to keep lower 8 bits and r3, r1, r4 # Keep only lower 8 bits of r1
Clear High Bits
# Clear upper 16 bits lis r4, 0x0000 # Load 0x00000000 into upper 16 bits ori r4, r4, 0xFFFF # Set lower 16 bits to 1 and r3, r1, r4 # r3 = r1 & 0x0000FFFF
Test Bit Pattern
# Test if specific bits are set li r4, 0x8000 # Test bit 0 (sign bit) and. r3, r1, r4 # Test and set condition codes beq bit_clear # Branch if bit was clear
Copy Register
# Copy register using AND with all 1s li r4, -1 # Load 0xFFFFFFFF and r3, r1, r4 # r3 = r1 (copy operation)