andi.
AND Immediate - 70 00 00 00
andi.
Instruction Syntax
| Mnemonic | Format | Description |
| andi. | rA,rS,UIMM | AND immediate and record |
Instruction Encoding
0
1
1
1
0
0
S
S
S
S
S
A
A
A
A
A
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
| Field | Bits | Description |
| Primary Opcode | 0-5 | 011100 (0x1C) |
| rS | 6-10 | Source register S |
| rA | 11-15 | Destination register A |
| UIMM | 16-31 | 16-bit unsigned immediate value |
Operation
rA ← (rS) & (0x0000 || UIMM)
The bitwise AND of the contents of rS and the zero-extended immediate value is placed into rA.
Note: The andi. instruction always updates the condition register field CR0. The immediate value is zero-extended (padded with zeros in the upper 16 bits).
Affected Registers
Condition Register (CR0 field)
(always)
- LT (Less Than)
- GT (Greater Than)
- EQ (Equal)
- SO (Summary Overflow)
For more information on condition codes see Section 2.1.3, "Condition Register," in the PowerPC Microprocessor Family: The Programming Environments manual.
Examples
Basic AND Immediate
andi. r3, r1, 0x00FF # r3 = r1 & 0x000000FF, set CR0
Extract Low Bits
# Extract lower 8 bits and test andi. r3, r1, 0x00FF # Keep only bits 24-31, set condition codes beq zero_result # Branch if result is zero
Test Individual Bits
# Test bit 31 (LSB) andi. r3, r1, 0x0001 # Test if bit 31 is set bne bit_set # Branch if bit was set # Test bit 16 andi. r3, r1, 0x8000 # Test if bit 16 is set
Clear High Bits
# Clear upper 16 bits, keep lower 16 bits andi. r3, r1, 0xFFFF # r3 = r1 & 0x0000FFFF
Bit Masking with Condition Test
# Mask and test specific bit pattern andi. r3, r1, 0x000E # Extract bits 28-30 cmpi cr1, 0, r3, 6 # Compare with expected pattern beq cr1, pattern_match # Branch if pattern matches
Quick Zero Test
# Test if any bits in lower 16 bits are set andi. r3, r1, 0xFFFF # AND with all lower bits beq all_clear # Branch if no bits set in lower 16