andis.
AND Immediate Shifted - 74 00 00 00
andis.
Instruction Syntax
| Mnemonic | Format | Description |
| andis. | rA,rS,UIMM | AND immediate shifted and record |
Instruction Encoding
0
1
1
1
0
1
S
S
S
S
S
A
A
A
A
A
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
| Field | Bits | Description |
| Primary Opcode | 0-5 | 011101 (0x1D) |
| rS | 6-10 | Source register S |
| rA | 11-15 | Destination register A |
| UIMM | 16-31 | 16-bit unsigned immediate value |
Operation
rA ← (rS) & (UIMM || 0x0000)
The bitwise AND of the contents of rS and the immediate value shifted left 16 bits (concatenated with 16 zero bits) is placed into rA.
Note: The andis. instruction always updates the condition register field CR0. The immediate value is shifted left 16 bits before the AND operation.
Affected Registers
Condition Register (CR0 field)
(always)
- LT (Less Than)
- GT (Greater Than)
- EQ (Equal)
- SO (Summary Overflow)
For more information on condition codes see Section 2.1.3, "Condition Register," in the PowerPC Microprocessor Family: The Programming Environments manual.
Examples
Basic AND Immediate Shifted
andis. r3, r1, 0xFF00 # r3 = r1 & 0xFF000000, set CR0
Test High Bits
# Test upper 8 bits andis. r3, r1, 0xFF00 # Keep only bits 0-7, set condition codes beq high_clear # Branch if upper 8 bits are clear
Extract High Word Bits
# Extract specific bits from upper 16 bits andis. r3, r1, 0x8000 # Test bit 0 (sign bit) bne negative # Branch if sign bit is set # Test bits 8-11 andis. r3, r1, 0x0F00 # Extract bits 8-11
Clear Low Bits, Keep High
# Keep only upper 16 bits andis. r3, r1, 0xFFFF # r3 = r1 & 0xFFFF0000
Test Address Range
# Test if address is in specific range (e.g., 0x8000xxxx) andis. r3, r1, 0x8000 # Test if address starts with 0x8000 bne in_range # Branch if in kernel space
Mask High Nibble
# Extract highest nibble (bits 0-3) andis. r3, r1, 0xF000 # r3 = r1 & 0xF0000000 srwi r3, r3, 28 # Shift to get nibble value in bits 28-31