Instruction Syntax

Mnemonic	Format	Flags
andc	rA,rS,rB	Rc = 0
andc.	rA,rS,rB	Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rS	6-10	Source register S
rA	11-15	Destination register A
rB	16-20	Source register B
Reserved	21	Should be zero
XO	22-29	60 (Extended opcode)
Rc	30-31	Record Condition Register

Operation

rA ← (rS) & ¬(rB)

The bitwise AND of the contents of rS and the complement of rB is placed into rA.

Note: This instruction ANDs the first operand with the bitwise complement (NOT) of the second operand.

Affected Registers

Condition Register (CR0 field)

(if Rc = 1)

• LT (Less Than)
• GT (Greater Than)
• EQ (Equal)
• SO (Summary Overflow)

For more information on condition codes see Section 2.1.3, "Condition Register," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic AND with Complement

andc r3, r1, r2    # r3 = r1 & (~r2)
andc. r3, r1, r2   # Same as above, but also sets condition register

Clear Specific Bits

# Clear bits 8-15 (using mask in r2 = 0x0000FF00)
li r2, 0xFF00      # Load bits to clear
andc r3, r1, r2    # Clear bits 8-15 in r1, result in r3

Selective Bit Clearing

# Clear only the bits that are set in r2
andc r3, r1, r2    # Keep bits in r1 where r2 bits are 0

Implement Subtract Operation

# Use andc as part of subtraction (r1 - r2)
andc r3, r1, r2    # r3 = r1 & (~r2)
# This is equivalent to clearing bits in r1 that are set in r2

Create Inverted Mask

# Keep all bits except those specified in mask
li r2, 0x000F      # Mask for bits 28-31
andc r3, r1, r2    # Keep all bits except 28-31

Related Instructions

and, andi., andis., or, orc