Instruction Syntax

Mnemonic	Format	Flags
divwu	rD,rA,rB	OE = 0, Rc = 0
divwu.	rD,rA,rB	OE = 0, Rc = 1
divwuo	rD,rA,rB	OE = 1, Rc = 0
divwuo.	rD,rA,rB	OE = 1, Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rD	6-10	Destination register
rA	11-15	Dividend register
rB	16-20	Divisor register
OE	21	Overflow Exception
XO	22-30	111001011 (459)
Rc	31	Record Condition Register

Operation

rD ← (rA) ÷ (rB)

The unsigned contents of register rA are divided by the unsigned contents of register rB. The unsigned quotient is placed in register rD. Both operands and the result are interpreted as 32-bit unsigned integers.

Note: Division by zero causes overflow. The result is undefined if the quotient cannot be represented in 32 bits.

Affected Registers

Condition Register (CR0 field)

(if Rc = 1)

• LT (Less Than) - undefined for unsigned division
• GT (Greater Than)
• EQ (Equal)
• SO (Summary Overflow)

Note: CR0 field may not reflect the correct comparison if overflow occurs (see XER below).

XER (Exception Register)

(if OE = 1)

• SO (Summary Overflow)
• OV (Overflow)

Overflow occurs when the divisor (rB) is zero.

For more information on condition codes see Section 2.1.3, "Condition Register," and Section 2.1.5, "XER Register," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic Unsigned Division

li r4, 200          # Dividend = 200
li r5, 8            # Divisor = 8
divwu r3, r4, r5    # r3 = 200 / 8 = 25

Large Unsigned Division

lis r4, 0x8000      # Load high part (0x80000000)
ori r4, r4, 0x0000  # Complete large unsigned value
li r5, 4            # Divisor = 4
divwu r3, r4, r5    # r3 = 0x80000000 / 4 = 0x20000000

Division with Condition Register

li r4, 100          # Dividend
li r5, 3            # Divisor
divwu. r3, r4, r5   # r3 = 100 / 3 = 33, sets CR0
# CR0[GT] = 1, CR0[EQ] = 0

Division with Overflow Detection

li r4, 500          # Dividend
li r5, 0            # Divisor = 0 (will cause overflow)
divwuo r3, r4, r5   # Division by zero, sets XER[OV] and XER[SO]
# Result is undefined, overflow exception may occur

Safe Unsigned Division

# Safe unsigned division with zero check
lwz r4, u_dividend  # Load unsigned dividend
lwz r5, u_divisor   # Load unsigned divisor
cmpwi r5, 0         # Check if divisor is zero
beq udiv_by_zero    # Branch if zero
divwu r3, r4, r5    # Perform unsigned division
b udiv_done         # Skip error handling

udiv_by_zero:
li r3, 0xFFFFFFFF   # Set result to max value for zero division
# Or handle error as appropriate

udiv_done:
# Continue with result in r3

Unsigned Division with Remainder

# Calculate both quotient and remainder for unsigned values
li r4, 50           # Dividend = 50
li r5, 7            # Divisor = 7
divwu r3, r4, r5    # r3 = quotient = 7
mullw r6, r3, r5    # r6 = quotient * divisor = 49
subf r7, r6, r4     # r7 = remainder = 50 - 49 = 1

Address Calculation with Division

# Calculate array index from byte offset
lwz r4, byte_offset # Load byte offset
li r5, 4            # Element size (4 bytes)
divwu r3, r4, r5    # r3 = element index = offset / size
# Use r3 as array index

Percentage Calculation

# Calculate percentage (unsigned)
lwz r4, partial_value   # Load partial value
lwz r5, total_value     # Load total value
mulli r4, r4, 100       # Multiply by 100 for percentage
divwu r3, r4, r5        # r3 = (partial * 100) / total = percentage

Related Instructions

divw, mullw, mulhwu, subf