Instruction Syntax

Mnemonic	Format	Flags
extsh	rA,rS	Rc = 0
extsh.	rA,rS	Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rS	6-10	Source register S
rA	11-15	Destination register A
Reserved	16-20	00000
Reserved	21	0
XO	22-30	1110011010 (922)
Rc	31	Record Condition Register

Operation

rA ← EXTS(rS[16-31])

The least significant halfword of rS (bits 16-31) is sign-extended to 32 bits and placed into rA. If bit 16 of rS is 0, then bits 0-15 of rA are set to 0. If bit 16 of rS is 1, then bits 0-15 of rA are set to 1.

Note: This instruction is used to convert signed 16-bit values to signed 32-bit values.

Affected Registers

Condition Register (CR0 field)

(if Rc = 1)

• LT (Less Than)
• GT (Greater Than)
• EQ (Equal)
• SO (Summary Overflow)

For more information on condition codes see Section 2.1.3, "Condition Register," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic Sign Extension

li r1, 0x8000       # Load positive halfword (0x8000 = 32768 unsigned)
extsh r2, r1        # r2 = 0xFFFF8000 (-32768 signed)

li r3, 0x7FFF       # Load positive halfword (0x7FFF = 32767)
extsh r4, r3        # r4 = 0x00007FFF (+32767 signed)

Converting Signed Short Values

# Load a signed short and extend to word
lhz r1, short_value(r0) # Load unsigned halfword
extsh r2, r1            # Sign extend to 32-bit signed value
# r2 now contains proper signed 32-bit representation

Array Processing with Sign Extension

# Process array of signed shorts
lis r3, signed_shorts@ha
addi r3, r3, signed_shorts@l
li r4, 0                # Index counter (in bytes)
li r5, 20               # Array size in bytes (10 shorts)

process_loop:
    lhzx r1, r3, r4     # Load halfword from array
    extsh r1, r1        # Sign extend to 32 bits
    # Process the signed value in r1
    addi r4, r4, 2      # Next element (2 bytes per short)
    cmpw r4, r5         # Check if done
    blt process_loop    # Continue if more elements

Sign Extension with Condition Check

lhz r1, input_short(r0) # Load halfword value
extsh. r2, r1           # Sign extend and set condition register
blt negative_value      # Branch if result is negative
beq zero_value          # Branch if result is zero
bgt positive_value      # Branch if result is positive

Audio Sample Processing

# Process 16-bit audio samples
lis r3, audio_buffer@ha
addi r3, r3, audio_buffer@l
li r4, 0                # Sample index
li r5, 1024             # Number of samples

audio_loop:
    lhzx r1, r3, r4     # Load 16-bit audio sample
    extsh r1, r1        # Sign extend to 32-bit signed
    # Apply audio processing to r1
    slwi r4, r4, 1      # Next sample (2 bytes each)
    addi r5, r5, -1     # Decrement counter
    cmpwi r5, 0         # Check if done
    bgt audio_loop      # Continue if more samples

Network Protocol Decoding

# Decode signed 16-bit network value
lis r3, packet@ha
addi r3, r3, packet@l
lhz r1, field_offset(r3) # Load 16-bit field from packet
extsh r2, r1             # Sign extend to 32-bit signed value
stw r2, decoded_field(r0) # Store decoded value

Arithmetic with Short Values

# Add signed short values correctly
lhz r1, value1(r0)      # Load first signed short
lhz r2, value2(r0)      # Load second signed short
extsh r1, r1            # Sign extend first value
extsh r2, r2            # Sign extend second value
add r3, r1, r2          # Add as 32-bit signed values
# Result in r3 is correct signed sum

Graphics Coordinate Processing

# Process signed 16-bit coordinates
lhz r1, x_coord(r0)     # Load X coordinate (signed 16-bit)
lhz r2, y_coord(r0)     # Load Y coordinate (signed 16-bit)
extsh r1, r1            # Sign extend X to 32-bit
extsh r2, r2            # Sign extend Y to 32-bit
# r1 and r2 now contain proper signed coordinates
# Range: -32768 to +32767 for each axis

Related Instructions

extsb, lhz, lhzx, sth