Instruction Syntax

Mnemonic	Format	Flags
fadd	frD,frA,frB	Rc = 0
fadd.	frD,frA,frB	Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	111111 (0x3F)
frD	6-10	Destination floating-point register
frA	11-15	Source floating-point register A
frB	16-20	Source floating-point register B
Reserved	21-25	00000
XO	26-30	10101 (21)
Rc	31	Record Condition Register

Operation

frD ← (frA) + (frB)

The contents of floating-point register frA are added to the contents of floating-point register frB. The result is placed into floating-point register frD.

Note: Both operands and the result are in double-precision format. The addition follows IEEE-754 standard for floating-point arithmetic.

Affected Registers

Condition Register (CR1 field)

(if Rc = 1)

• Reflects floating-point exception summary and status

Floating-Point Status and Control Register (FPSCR)

Affected fields:

• FPRF (Floating-Point Result Flags)
• FX (Floating-Point Exception Summary)
• OX (Overflow Exception)
• UX (Underflow Exception)
• XX (Inexact Exception)
• VXISI (Invalid Operation Exception for ∞ - ∞)
• FR (Fraction Rounded)
• FI (Fraction Inexact)

For more information on floating-point status see Section 2.1.4, "Floating-Point Status and Control Register (FPSCR)," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic Floating-Point Addition

lfd f1, value_a(r0)        # Load first operand
lfd f2, value_b(r0)        # Load second operand
fadd f3, f1, f2            # f3 = f1 + f2
stfd f3, result(r0)        # Store result

Addition with Condition Recording

lfd f1, input1(r0)         # Load first input
lfd f2, input2(r0)         # Load second input
fadd. f3, f1, f2           # f3 = f1 + f2, set CR1 with FP status
# CR1 now reflects floating-point exception status

Vector Addition

# Add corresponding components of two 3D vectors
lfd f1, vector1_x(r0)      # Load vector1.x
lfd f2, vector1_y(r0)      # Load vector1.y
lfd f3, vector1_z(r0)      # Load vector1.z
lfd f4, vector2_x(r0)      # Load vector2.x
lfd f5, vector2_y(r0)      # Load vector2.y
lfd f6, vector2_z(r0)      # Load vector2.z
fadd f7, f1, f4            # result.x = vector1.x + vector2.x
fadd f8, f2, f5            # result.y = vector1.y + vector2.y
fadd f9, f3, f6            # result.z = vector1.z + vector2.z

Accumulator Pattern

# Sum elements in an array
lfd f1, initial_sum(r0)    # Load initial sum (often 0.0)
lis r3, array@ha           # Load array address
addi r3, r3, array@l
li r4, 10                  # Array size

sum_loop:
    lfdx f2, r3, r5        # Load array element
    fadd f1, f1, f2        # Add to accumulator
    addi r5, r5, 8         # Next element (8 bytes per double)
    addic. r4, r4, -1      # Decrement counter
    bne sum_loop           # Continue if more elements
# f1 now contains the sum

Mathematical Expression

# Calculate: result = (a + b) + (c + d)
lfd f1, a(r0)              # Load a
lfd f2, b(r0)              # Load b
lfd f3, c(r0)              # Load c
lfd f4, d(r0)              # Load d
fadd f5, f1, f2            # f5 = a + b
fadd f6, f3, f4            # f6 = c + d
fadd f7, f5, f6            # f7 = (a + b) + (c + d)

Complex Number Addition

# Add two complex numbers: (a + bi) + (c + di)
lfd f1, complex1_real(r0)  # Load real part of first complex
lfd f2, complex1_imag(r0)  # Load imaginary part of first complex
lfd f3, complex2_real(r0)  # Load real part of second complex
lfd f4, complex2_imag(r0)  # Load imaginary part of second complex
fadd f5, f1, f3            # Real part: a + c
fadd f6, f2, f4            # Imaginary part: b + d
# Result: f5 + f6*i

Related Instructions

fadds, fsub, fsubs, fmul, fdiv