FADDS - Floating Add Single Instruction | PowerPC Instruction Set Reference

Instruction Syntax

Mnemonic	Format	Flags
fadds	frD,frA,frB	Rc = 0
fadds.	frD,frA,frB	Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	111011 (0x3B)
frD	6-10	Destination floating-point register
frA	11-15	Source floating-point register A
frB	16-20	Source floating-point register B
Reserved	21-25	00000
XO	26-30	10101 (21)
Rc	31	Record Condition Register

Operation

frD ← SINGLE((frA) + (frB))

The contents of floating-point register frA are added to the contents of floating-point register frB. The result is rounded to single-precision and placed into floating-point register frD.

Note: Both operands are converted to single-precision format before the operation, and the result is in single-precision format (stored in double-precision format in the FPR). The addition follows IEEE-754 standard for single-precision floating-point arithmetic.

Affected Registers

Condition Register (CR1 field)

(if Rc = 1)

Reflects floating-point exception summary and status

Floating-Point Status and Control Register (FPSCR)

Affected fields:

FPRF (Floating-Point Result Flags)
FX (Floating-Point Exception Summary)
OX (Overflow Exception)
UX (Underflow Exception)
XX (Inexact Exception)
VXISI (Invalid Operation Exception for ∞ - ∞)
FR (Fraction Rounded)
FI (Fraction Inexact)

For more information on floating-point status see Section 2.1.4, "Floating-Point Status and Control Register (FPSCR)," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic Single-Precision Addition

lfs f1, float_a(r0)        # Load first single-precision operand
lfs f2, float_b(r0)        # Load second single-precision operand
fadds f3, f1, f2           # f3 = f1 + f2 (single-precision)
stfs f3, result(r0)        # Store single-precision result

Single-Precision with Condition Recording

lfs f1, input1(r0)         # Load first input
lfs f2, input2(r0)         # Load second input
fadds. f3, f1, f2          # f3 = f1 + f2, set CR1 with FP status
# CR1 now reflects floating-point exception status

Mixed Precision Operations

# Add double-precision values with single-precision result
lfd f1, double_a(r0)       # Load double-precision value
lfd f2, double_b(r0)       # Load double-precision value
fadds f3, f1, f2           # Add and round to single-precision
stfs f3, single_result(r0) # Store as single-precision

Performance-Optimized Vector Addition

# Single-precision 3D vector addition (faster than double)
lfs f1, vector1_x(r0)      # Load vector1.x (single)
lfs f2, vector1_y(r0)      # Load vector1.y (single)
lfs f3, vector1_z(r0)      # Load vector1.z (single)
lfs f4, vector2_x(r0)      # Load vector2.x (single)
lfs f5, vector2_y(r0)      # Load vector2.y (single)
lfs f6, vector2_z(r0)      # Load vector2.z (single)
fadds f7, f1, f4           # result.x = vector1.x + vector2.x
fadds f8, f2, f5           # result.y = vector1.y + vector2.y
fadds f9, f3, f6           # result.z = vector1.z + vector2.z

Graphics/Game Processing

# Color channel blending (single-precision for speed)
lfs f1, color1_red(r0)     # Load red channel of color1
lfs f2, color1_green(r0)   # Load green channel of color1
lfs f3, color1_blue(r0)    # Load blue channel of color1
lfs f4, color2_red(r0)     # Load red channel of color2
lfs f5, color2_green(r0)   # Load green channel of color2
lfs f6, color2_blue(r0)    # Load blue channel of color2
fadds f7, f1, f4           # Blend red channels
fadds f8, f2, f5           # Blend green channels
fadds f9, f3, f6           # Blend blue channels

Audio Processing

# Mix two audio samples (single-precision)
lfs f1, sample1(r0)        # Load first audio sample
lfs f2, sample2(r0)        # Load second audio sample
fadds f3, f1, f2           # Mix samples
# Apply gain control
lfs f4, gain_factor(r0)    # Load gain
fmuls f3, f3, f4           # Apply gain
stfs f3, mixed_output(r0)  # Store mixed result

Single-Precision Array Processing

# Sum single-precision array elements
lfs f1, initial_sum(r0)    # Load initial sum (0.0f)
lis r3, array@ha           # Load array address
addi r3, r3, array@l
li r4, 20                  # Array size

sum_loop:
    lfsx f2, r3, r5        # Load array element (single)
    fadds f1, f1, f2       # Add to accumulator
    addi r5, r5, 4         # Next element (4 bytes per float)
    addic. r4, r4, -1      # Decrement counter
    bne sum_loop           # Continue if more elements
# f1 now contains the single-precision sum

Related Instructions

fadd, fsubs, fmuls, fdivs, frsp

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