Instruction Syntax

Mnemonic	Format	Flags
lwarx	rD,rA,rB	None

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rD	6-10	Destination register
rA	11-15	Base register (can be 0)
rB	16-20	Index register
XO	21-30	0000000001 (1) - Extended opcode
Rc	31	Record bit (0)

Operation

if rA = 0 then EA ← (rB)
else EA ← (rA) + (rB)
rD ← MEM(EA, 4)
Reserve ← EA

A word (32 bits) is loaded from memory and placed in register rD. The effective address is computed by adding the contents of registers rA and rB, or just rB if rA is 0. A reservation is established on the memory location specified by the effective address.

Note: This instruction is part of the PowerPC atomic operation mechanism. The reservation is used to ensure that a subsequent stwcx. instruction will succeed only if no other processor has modified the reserved memory location. This enables the implementation of atomic read-modify-write operations without requiring explicit locking.

Affected Registers

• rD: Loaded with word value from memory
• rA: Used as base register (if not 0)
• rB: Used as index register
• Reserve: Internal reservation mechanism

Examples

Example 1: Atomic increment

# Atomic increment of a counter
loop:
    lwarx r3, 0, r4    # Load and reserve counter value
    addi r3, r3, 1     # Increment the value
    stwcx. r3, 0, r4   # Try to store, check if reservation still valid
    bne- loop          # If store failed, retry

Example 2: Atomic compare and swap

# Atomic compare and swap operation
loop:
    lwarx r5, 0, r6    # Load and reserve current value
    cmpw r5, r7        # Compare with expected value
    bne done           # If not equal, exit
    stwcx. r8, 0, r6   # Try to store new value
    bne- loop          # If store failed, retry
done:

Example 3: Atomic bit manipulation

# Atomic bit set operation
loop:
    lwarx r9, 0, r10   # Load and reserve word
    ori r9, r9, 0x80   # Set bit 7
    stwcx. r9, 0, r10  # Try to store modified value
    bne- loop          # If store failed, retry

Related Instructions

stwcx., lwz, lwzx, sync