Instruction Syntax

Mnemonic	Format	Flags
mtcrf	CRM,rS	None

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rS	6-10	Source register
CRM	11-18	Condition Register Mask
Reserved	19-30	Should be zero
Reserved	31	Should be zero

Operation

for i = 0 to 7
    if CRM[i] = 1 then
        CR[4×i:4×i+3] ← rS[4×i:4×i+3]
    endif
endfor

The contents of general-purpose register rS are conditionally copied to the Condition Register (CR) based on the Condition Register Mask (CRM). Each bit in the CRM controls whether the corresponding 4-bit CR field is updated.

Note: This instruction allows selective updating of condition register fields. Only the fields corresponding to set bits in the CRM are modified, preserving the contents of other CR fields.

Affected Registers

Condition Register (CR)

(conditional)

• CR fields - Updated based on CRM mask bits

General Purpose Registers (GPRs)

(read only)

• rS - Source register (read only)

For more information on condition codes see Section 2.1.3, "Condition Register," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Update Single CR Field

# Update only CR0 with value from r3
li r3, 0x80000000     # Set LT bit (negative)
mtcrf 0x80, r3        # Update only CR0 (bit 7 of CRM)
# CR0 now contains LT=1, GT=0, EQ=0, SO=0

Update Multiple CR Fields

# Update CR0 and CR1 with values from r4
li r4, 0x80008000     # Set LT bits in both fields
mtcrf 0xC0, r4        # Update CR0 and CR1 (bits 7,6 of CRM)
# CR0 and CR1 now have LT=1, others=0

Preserve CR Fields

# Update only CR7, preserve all others
li r5, 0x00000080     # Set SO bit in field 7
mtcrf 0x01, r5        # Update only CR7 (bit 0 of CRM)
# Only CR7 is modified, others unchanged

Conditional Logic

# Set up multiple condition codes
cmpwi cr0, r6, 0      # Compare r6 with 0
cmpwi cr1, r7, 100    # Compare r7 with 100
cmpwi cr2, r8, -50    # Compare r8 with -50

# Save all condition codes to r9
mfcr r9               # Move CR to r9

# ... perform other operations ...

# Restore specific condition codes
mtcrf 0xE0, r9        # Restore CR0, CR1, CR2 (bits 7,6,5)
# CR3-CR7 remain unchanged

Function Return Status

# Function returns status in r3
function_call:
    bl some_function   # Call function
    mtcrf 0x80, r3     # Move return status to CR0
    beq cr0, success   # Check if successful
    b error_handler    # Handle error

Error Code Processing

# Process error codes in different CR fields
li r10, 0x12345678    # Error code with multiple status bits
mtcrf 0xFF, r10       # Update all CR fields
# Each CR field now contains 4 bits of error information

State Machine

# State machine using CR fields
li r11, 0x00000001    # State 1
mtcrf 0x80, r11       # Set state in CR0

# Check current state
bt cr0, state_1       # Branch if in state 1
bt cr1, state_2       # Branch if in state 2
bt cr2, state_3       # Branch if in state 3

Flag Management

# Manage multiple flags in CR fields
li r12, 0x80004002    # Various flags
mtcrf 0x0F, r12       # Update CR0-CR3
# CR0: LT=1, CR1: GT=1, CR2: EQ=1, CR3: SO=1

Interrupt Status

# Save interrupt status
mfspr r13, 8          # Get interrupt status
mtcrf 0x10, r13       # Save in CR4
# CR4 now contains interrupt status bits

Debug Information

# Store debug information in CR
li r14, 0xDEADBEEF    # Debug value
mtcrf 0x07, r14       # Store in CR0-CR2
# CR fields contain debug information

Related Instructions

mcrf, mcrfs, mcrxr, mfcr