Instruction Syntax

Mnemonic	Format	Flags
mcrfs	crfD,crfS	None

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
crfD	6-8	Destination condition register field
Reserved	9-10	Should be zero
crfS	11-13	Source FPSCR field number
Reserved	14-20	Should be zero
XO	21-30	0x0A4 (164) - Extended opcode
Reserved	31	Should be zero

Operation

CR[4×crfD:4×crfD+3] ← FPSCR[4×crfS:4×crfS+3]

The contents of the specified FPSCR field (crfS) are copied to the destination condition register field (crfD). The FPSCR fields correspond to different floating-point status conditions such as exception flags and result flags.

Note: This instruction provides a bridge between floating-point and integer code by allowing integer conditional branches to test floating-point status conditions. The FPSCR field numbers correspond to specific floating-point status bits.

Affected Registers

Condition Register (CR)

(always)

• CR[crfD] - Destination condition register field (LT, GT, EQ, SO bits)

Floating-Point Status and Control Register (FPSCR)

(read only)

• FPSCR - Source register (read only)

For more information on floating-point status see Section 2.1.4, "Floating-Point Status and Control Register (FPSCR)," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Check Floating-Point Exception Status

# Check if floating-point exception occurred
fadd f1, f2, f3          # Perform floating-point addition
mcrfs cr1, 0             # Copy FPSCR exception flags to CR1
bt cr1, handle_fp_exception # Branch if exception occurred

Test Floating-Point Result Flags

# Test floating-point result after operation
fmul f1, f2, f3          # Perform floating-point multiplication
mcrfs cr2, 1             # Copy FPSCR result flags to CR2
beq cr2, result_zero     # Branch if result is zero
blt cr2, result_negative # Branch if result is negative

Check Overflow Condition

# Check for floating-point overflow
fadd f1, f2, f3          # Add large floating-point numbers
mcrfs cr3, 0             # Copy FPSCR to CR3
bt cr3, overflow_detected # Branch if overflow occurred

Test for NaN Result

# Check if result is NaN
fdiv f1, f2, f3          # Perform division (might produce NaN)
mcrfs cr4, 1             # Copy FPSCR result flags to CR4
bt cr4, nan_detected     # Branch if NaN detected

Check Underflow Condition

# Check for floating-point underflow
fmul f1, f2, f3          # Multiply small numbers
mcrfs cr5, 0             # Copy FPSCR to CR5
bt cr5, underflow_detected # Branch if underflow occurred

Test Inexact Result

# Check if result was rounded
fadd f1, f2, f3          # Add floating-point numbers
mcrfs cr6, 0             # Copy FPSCR to CR6
bt cr6, inexact_result   # Branch if result was inexact

Check Invalid Operation

# Check for invalid floating-point operation
fsqrt f1, f2             # Square root of negative number
mcrfs cr7, 0             # Copy FPSCR to CR7
bt cr7, invalid_operation # Branch if invalid operation

Multiple Floating-Point Status Checks

# Check multiple floating-point conditions
fadd f1, f2, f3          # Perform floating-point operation
mcrfs cr1, 0             # Copy exception flags
mcrfs cr2, 1             # Copy result flags

# Test different conditions
bt cr1, exception_occurred # Check for exceptions
beq cr2, result_is_zero   # Check if result is zero
blt cr2, result_negative  # Check if result is negative

Floating-Point Error Handling

# Comprehensive floating-point error handling
fdiv f1, f2, f3          # Perform division
mcrfs cr1, 0             # Get exception status

# Check for specific error conditions
bt cr1, division_error   # Branch if division error
bt cr1, overflow_error   # Branch if overflow
bt cr1, underflow_error  # Branch if underflow
bt cr1, inexact_error    # Branch if inexact result

Floating-Point Validation

# Validate floating-point input values
fadd f1, f2, f3          # Test operation with inputs
mcrfs cr1, 0             # Get status

# Check if inputs were valid
bt cr1, invalid_inputs   # Branch if inputs caused exception
# Continue with valid result if no exception

Related Instructions

mcrf, mcrxr, mffs, mtfsf