Instruction Syntax

Mnemonic	Format	Flags
mtfsf	FM,fB	Rc = 0
mtfsf.	FM,fB	Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	111111 (0x3F)
Reserved	6-10	Should be zero
Reserved	11-15	Should be zero
Reserved	16-20	Should be zero
fB	21-25	Source floating-point register
XO	26-30	00010 (2)
Rc	31	Record Condition Register

Operation

FPSCR ← (FPSCR & ~FM) | (fB & FM)

Updates the Floating-Point Status and Control Register (FPSCR) based on the field mask FM and source register fB.

Note: The mtfsf instruction allows selective updating of FPSCR fields. Only the fields corresponding to set bits in the FM are modified, preserving the contents of other FPSCR fields.

Affected Registers

Floating-Point Status and Control Register (FPSCR)

(conditional)

• FPSCR fields - Updated based on FM mask bits

Floating-Point Registers (FPRs)

(read only)

• fB - Source floating-point register (read only)

Condition Register (CR1 field)

(if Rc = 1)

• Reflects floating-point exception summary and status

For more information on floating-point status see Section 2.1.4, "Floating-Point Status and Control Register (FPSCR)," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Update Exception Flags

# Update only exception flags from f1
mtfsf 0xFF, f1        # Update all exception flags
mtfsf 0x0F, f2        # Update only exception flags (bits 0-3)

Selective Field Update

# Update only rounding mode and exception enable bits
mtfsf 0x30, f3        # Update bits 4-5 (rounding mode)
mtfsf 0x0F, f4        # Update exception enable bits (bits 0-3)

Conditional Update

# Update FPSCR only if condition is met
cmpwi r3, 0           # Check if r3 is zero
beq update_fpscr      # Branch if zero
b skip_update         # Skip update
update_fpscr:
mtfsf 0xFF, f5        # Update all fields
skip_update:

Related Instructions

mtfsb0, mtfsb1, mtfsfi