Instruction Syntax

Mnemonic	Format	Flags
mtfsb0	crfD	Rc = 0
mtfsb0.	crfD	Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	111111 (0x3F)
Reserved	6-10	Should be zero
Reserved	11-15	Should be zero
Reserved	16-20	Should be zero
Reserved	21-25	Should be zero
XO	26-30	00001 (1)
Rc	31	Record Condition Register

Operation

FPSCR[crfD] ← 0

Clears the specified bit in the Floating-Point Status and Control Register (FPSCR).

Note: The mtfsb0 instruction clears a specific bit in the FPSCR. This is useful for resetting floating-point exception flags or control bits.

Affected Registers

Floating-Point Status and Control Register (FPSCR)

(always)

• FPSCR[crfD] - Cleared to 0

Condition Register (CR1 field)

(if Rc = 1)

• Reflects floating-point exception summary and status

For more information on floating-point status see Section 2.1.4, "Floating-Point Status and Control Register (FPSCR)," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Clear Exception Flag

mtfsb0 0              # Clear bit 0 (Invalid Operation flag)
mtfsb0. 1             # Clear bit 1 and set condition register

Reset FPSCR Bits

# Clear multiple exception flags
mtfsb0 0              # Clear Invalid Operation
mtfsb0 1              # Clear Overflow
mtfsb0 2              # Clear Underflow
mtfsb0 3              # Clear Division by Zero

Conditional Clearing

# Clear flag only if condition is met
cmpwi r3, 0           # Check if r3 is zero
beq clear_flag        # Branch if zero
b skip_clear          # Skip clearing
clear_flag:
mtfsb0 5              # Clear bit 5
skip_clear:

Related Instructions

mtfsb1, mtfsf, mtfsfi