Instruction Syntax

Mnemonic	Format	Flags
mtfsb1	crfD	Rc = 0
mtfsb1.	crfD	Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	111111 (0x3F)
Reserved	6-10	Should be zero
Reserved	11-15	Should be zero
Reserved	16-20	Should be zero
Reserved	21-25	Should be zero
XO	26-30	00010 (2)
Rc	31	Record Condition Register

Operation

FPSCR[crfD] ← 1

Sets the specified bit in the Floating-Point Status and Control Register (FPSCR).

Note: The mtfsb1 instruction sets a specific bit in the FPSCR. This is useful for setting floating-point exception flags or control bits.

Affected Registers

Floating-Point Status and Control Register (FPSCR)

(always)

• FPSCR[crfD] - Set to 1

Condition Register (CR1 field)

(if Rc = 1)

• Reflects floating-point exception summary and status

For more information on floating-point status see Section 2.1.4, "Floating-Point Status and Control Register (FPSCR)," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Set Exception Flag

mtfsb1 0              # Set bit 0 (Invalid Operation flag)
mtfsb1. 1             # Set bit 1 and set condition register

Set FPSCR Bits

# Set multiple exception flags
mtfsb1 0              # Set Invalid Operation
mtfsb1 1              # Set Overflow
mtfsb1 2              # Set Underflow
mtfsb1 3              # Set Division by Zero

Conditional Setting

# Set flag only if condition is met
cmpwi r3, 0           # Check if r3 is zero
bne set_flag          # Branch if not zero
b skip_set            # Skip setting
set_flag:
mtfsb1 5              # Set bit 5
skip_set:

Related Instructions

mtfsb0, mtfsf, mtfsfi