Instruction Syntax

Mnemonic	Format	Flags
mtfsfi	crfD,IMM	Rc = 0
mtfsfi.	crfD,IMM	Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	111111 (0x3F)
Reserved	6-10	Should be zero
Reserved	11-15	Should be zero
Reserved	16-20	Should be zero
Reserved	21-25	Should be zero
XO	26-30	00011 (3)
Rc	31	Record Condition Register

Operation

FPSCR[4×crfD:4×crfD+3] ← IMM

Sets the specified field in the Floating-Point Status and Control Register (FPSCR) to the immediate value.

Note: The mtfsfi instruction sets a 4-bit field in the FPSCR to an immediate value. This is useful for setting specific FPSCR fields without loading a value into a floating-point register first.

Affected Registers

Floating-Point Status and Control Register (FPSCR)

(always)

• FPSCR[4×crfD:4×crfD+3] - Set to immediate value

Condition Register (CR1 field)

(if Rc = 1)

• Reflects floating-point exception summary and status

For more information on floating-point status see Section 2.1.4, "Floating-Point Status and Control Register (FPSCR)," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Set Rounding Mode

mtfsfi 0, 0           # Set field 0 to 0 (round to nearest)
mtfsfi 0, 1           # Set field 0 to 1 (round toward zero)
mtfsfi 0, 2           # Set field 0 to 2 (round toward +infinity)
mtfsfi 0, 3           # Set field 0 to 3 (round toward -infinity)

Set Exception Flags

# Set specific exception flags
mtfsfi 1, 0x0         # Clear all exception flags in field 1
mtfsfi 1, 0xF         # Set all exception flags in field 1

Conditional Field Setting

# Set field only if condition is met
cmpwi r3, 0           # Check if r3 is zero
beq set_field         # Branch if zero
b skip_set            # Skip setting
set_field:
mtfsfi 2, 5           # Set field 2 to 5
skip_set:

Related Instructions

mtfsb0, mtfsb1, mtfsf