stfdu
Store Floating-Point Double with Update - DC 00 00 00
stfdu
Instruction Syntax
Mnemonic | Format | Flags |
stfdu | frS,d(rA) | None |
Instruction Encoding
1
1
0
1
1
1
S
S
S
S
S
A
A
A
A
A
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Field | Bits | Description |
Primary Opcode | 0-5 | 110111 (0x37) |
frS | 6-10 | Source floating-point register |
rA | 11-15 | Base register (updated) |
SIMM | 16-31 | Signed immediate offset |
Operation
EA ← (rA) + SIMM (EA) ← (frS) rA ← EA
The effective address is calculated by adding the signed immediate offset to the base register. The double-precision floating-point value in the source register is stored at the effective address. The base register is updated with the effective address.
Note: The stfdu instruction stores a 64-bit double-precision floating-point value to memory and updates the base register with the effective address. The address must be aligned to an 8-byte boundary.
Affected Registers
General Purpose Registers (GPRs)
- rA (Base register) - Updated with effective address
Memory
- Double-precision floating-point value at effective address (EA)
Examples
Basic Store Floating-Point Double with Update
# Store double-precision value and update base register stfdu fr1, 8(r3) # Store at r3 + 8, then r3 = r3 + 8
Array of Doubles with Auto-Increment
# Store doubles in array sequentially li r3, array # Load array base address li r4, 0 # Counter loop: stfdu fr1, 8(r3) # Store double, increment address by 8 addi r4, r4, 1 # Increment counter cmpwi r4, 10 # Check if done blt loop
Floating-Point Data Processing
# Process floating-point data with auto-increment li r3, data_buffer # Load data buffer address li r4, 0 # Counter process_loop: fadd fr2, fr0, fr1 # Calculate result stfdu fr2, 8(r3) # Store result, increment address addi r4, r4, 1 # Increment counter cmpwi r4, 100 # Check if done blt process_loop