Instruction Syntax

Mnemonic	Format	Flags
stfdux	frS,rA,rB	None

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
frS	6-10	Source floating-point register
rA	11-15	Base register (updated)
rB	16-20	Index register
Reserved	21-29	000000000
Reserved	30-31	00

Operation

EA ← (rA) + (rB)
(EA) ← (frS)
rA ← EA

The effective address is calculated by adding the base register to the index register. The double-precision floating-point value in the source register is stored at the effective address. The base register is updated with the effective address.

Note: The stfdux instruction stores a 64-bit double-precision floating-point value to memory and updates the base register with the effective address. The address must be aligned to an 8-byte boundary.

Affected Registers

General Purpose Registers (GPRs)

• rA (Base register) - Updated with effective address

Memory

• Double-precision floating-point value at effective address (EA)

Examples

Basic Store Floating-Point Double with Update Indexed

# Store double-precision value using indexed addressing with update
stfdux fr1, r3, r4   # Store fr1 at r3 + r4, then r3 = r3 + r4

Array of Doubles with Dynamic Index

# Store doubles in array using dynamic index
li r3, array         # Load array base address
li r4, 0             # Index = 0
stfdux fr1, r3, r4   # Store double, update base address

Floating-Point Data Processing

# Process floating-point data with dynamic addressing
li r3, data_buffer   # Load data buffer address
li r4, 0             # Index = 0
process_loop:
fadd fr2, fr0, fr1   # Calculate result
stfdux fr2, r3, r4   # Store result, update base address
addi r4, r4, 8       # Increment index by 8 bytes
cmpwi r4, 800        # Check if done (100 doubles * 8 bytes)
blt process_loop

Related Instructions

stfd, stfdu, stfdx, lfdux