Instruction Syntax
| Mnemonic | Format | Flags |
| eieio | - | - |
Instruction Encoding
| Field | Bits | Description |
| Primary Opcode | 0-5 | 011111 (0x1F) |
| Reserved | 6-10 | 00000 |
| Reserved | 11-15 | 00000 |
| Reserved | 16-20 | 00000 |
| Reserved | 21 | 0 |
| XO | 22-30 | 1101010110 (854) |
| Reserved | 31 | 0 |
Operation
Enforce ordering of memory-mapped I/O operations
The eieio instruction provides an ordering function for the effects of loads and stores executed by a processor on memory-mapped device registers. Specifically, eieio ensures that all applicable memory accesses caused by instructions preceding the eieio instruction are performed with respect to main storage before any applicable memory accesses caused by instructions following the eieio instruction.
Note: This instruction only orders memory-mapped I/O operations and cached memory operations that are marked as write-through required, caching-inhibited, or both.
Affected Registers
None - This instruction does not affect any registers.
For more information on memory ordering see Section 2.2, "Storage Model," in the PowerPC Microprocessor Family: The Programming Environments manual.
Examples
Basic I/O Ordering
# Ensure memory-mapped I/O write completes before next operation lis r3, mmio_base@ha addi r3, r3, mmio_base@l stw r4, 0(r3) # Write to memory-mapped register eieio # Ensure write completes before continuing lwz r5, 4(r3) # Read from next register
Device Register Sequence
# Configure device with proper ordering lis r3, device_regs@ha addi r3, r3, device_regs@l # Configure device control register li r4, 0x01 stw r4, ctrl_reg(r3) # Enable device eieio # Ensure control write completes # Configure data register li r5, 0x1234 stw r5, data_reg(r3) # Write data eieio # Ensure data write completes # Start operation li r6, 0x80 stw r6, cmd_reg(r3) # Start command
Interrupt Controller Programming
# Program interrupt controller with proper ordering lis r3, int_ctrl@ha addi r3, r3, int_ctrl@l # Disable interrupts first li r4, 0x00 stw r4, int_enable(r3) # Disable all interrupts eieio # Wait for disable to take effect # Clear pending interrupts li r5, 0xFF stw r5, int_clear(r3) # Clear all pending eieio # Wait for clear to complete # Re-enable specific interrupts li r6, 0x0F stw r6, int_enable(r3) # Enable specific interrupts
Cache Coherent I/O
# Ensure cache operations complete before I/O lis r3, dma_buffer@ha addi r3, r3, dma_buffer@l dcbf 0, r3 # Flush cache line to memory eieio # Ensure cache flush completes # Now safe to start DMA lis r4, dma_ctrl@ha addi r4, r4, dma_ctrl@l stw r3, dma_addr(r4) # Set DMA source address eieio # Ensure address write completes li r5, 0x01 stw r5, dma_start(r4) # Start DMA operation