dcbf
Data Cache Block Flush - 7C 00 00 AC
dcbf
Instruction Syntax
| Mnemonic | Format | Flags |
| dcbf | rA,rB | - |
Instruction Encoding
0
1
1
1
1
1
0
0
0
0
0
A
A
A
A
A
B
B
B
B
B
0
0
0
0
0
1
0
1
0
1
0
| Field | Bits | Description |
| Primary Opcode | 0-5 | 011111 (0x1F) |
| Reserved | 6-10 | 00000 |
| rA | 11-15 | Register A (base address) |
| rB | 16-20 | Register B (index) |
| Reserved | 21 | 0 |
| XO | 22-30 | 000010101 (21) |
| Reserved | 31 | 0 |
Operation
if rA = 0 then EA ← (rB) else EA ← (rA) + (rB)
Flush cache block containing EA to memory
The data cache block flush instruction forces any modified data in the cache block containing the effective address to be written to memory and marks the cache block as invalid. If the cache block is not modified, it is simply invalidated.
Note: This instruction ensures cache coherency by writing modified data to memory.
Affected Registers
None - This instruction does not affect any registers.
For more information on cache management see Section 3.2, "Cache Management Instructions," in the PowerPC Microprocessor Family: The Programming Environments manual.
Examples
Basic Cache Block Flush
# Flush a specific cache block to memory lis r3, data_buffer@ha # Load high part of buffer address addi r3, r3, data_buffer@l # Complete buffer address dcbf 0, r3 # Flush cache block to memory
Flush Multiple Cache Blocks
# Flush entire buffer to memory
lis r3, write_buffer@ha
addi r3, r3, write_buffer@l
li r4, 0 # Start offset
li r5, 1024 # Buffer size
li r6, 32 # Cache line size
flush_loop:
dcbf r3, r4 # Flush cache block
add r4, r4, r6 # Next cache line
cmpw r4, r5 # Check if done
blt flush_loop # Continue if more blocks
DMA Buffer Preparation
# Prepare buffer for DMA transfer by flushing to memory
lis r3, dma_buffer@ha
addi r3, r3, dma_buffer@l
li r4, 0
li r5, 4096 # DMA buffer size
dma_prep_loop:
dcbf r3, r4 # Flush cache block
addi r4, r4, 32 # Next cache line (32-byte lines)
cmpwi r4, r5 # Check bounds
blt dma_prep_loop # Continue until done
Memory-Mapped I/O Synchronization
# Ensure writes to memory-mapped I/O are visible lis r3, mmio_base@ha addi r3, r3, mmio_base@l stw r4, 0(r3) # Write to MMIO register dcbf 0, r3 # Force write to reach hardware sync # Ensure ordering