Instruction Syntax

Mnemonic	Format	Flags
dcbi	rA,rB	-

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
Reserved	6-10	00000
rA	11-15	Register A (base address)
rB	16-20	Register B (index)
Reserved	21	0
XO	22-30	111010110 (470)
Reserved	31	0

Operation

if rA = 0 then EA ← (rB)
else EA ← (rA) + (rB)

Invalidate cache block containing EA

The data cache block invalidate instruction marks the cache block containing the effective address as invalid without writing any modified data to memory. If the cache block contains modified data, that data is lost.

Note: This instruction is used when it is known that the cache contents are no longer valid or when the memory will be updated by another mechanism.

Affected Registers

None - This instruction does not affect any registers.

For more information on cache management see Section 3.2, "Cache Management Instructions," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic Cache Block Invalidate

# Invalidate a specific cache block
lis r3, data_buffer@ha  # Load high part of buffer address
addi r3, r3, data_buffer@l  # Complete buffer address
dcbi 0, r3              # Invalidate cache block

Invalidate Multiple Cache Blocks

# Invalidate entire buffer from cache
lis r3, stale_buffer@ha
addi r3, r3, stale_buffer@l
li r4, 0                # Start offset
li r5, 1024             # Buffer size
li r6, 32               # Cache line size

invalidate_loop:
    dcbi r3, r4         # Invalidate cache block
    add r4, r4, r6      # Next cache line
    cmpw r4, r5         # Check if done
    blt invalidate_loop # Continue if more blocks

Memory-Mapped I/O Cache Invalidation

# Invalidate cache for memory-mapped I/O region
lis r3, mmio_base@ha
addi r3, r3, mmio_base@l
li r4, 0
li r5, 256              # Size of MMIO region

mmio_invalidate_loop:
    dcbi r3, r4         # Invalidate cache block
    addi r4, r4, 32     # Next cache line (32-byte lines)
    cmpwi r4, r5        # Check bounds
    blt mmio_invalidate_loop # Continue until done

Preparing for DMA Operation

# Invalidate cache before DMA read operation
# (when DMA will overwrite the entire buffer)
lis r3, dma_buffer@ha
addi r3, r3, dma_buffer@l
dcbi 0, r3              # Invalidate first cache line
dcbi 32, r3             # Invalidate second cache line
# Continue for entire DMA buffer size

Related Instructions

dcba, dcbf, dcbst, dcbt, dcbtst, dcbz, sync