Instruction Syntax

Mnemonic	Format	Flags
dcba	rA,rB	-

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
Reserved	6-10	00000
rA	11-15	Register A (base address)
rB	16-20	Register B (index)
Reserved	21	0
XO	22-30	101110110 (374)
Reserved	31	0

Operation

if rA = 0 then EA ← (rB)
else EA ← (rA) + (rB)

Allocate cache block containing EA

The data cache block allocate instruction attempts to allocate a cache block at the effective address without loading data from memory. This is a hint to the processor that the program will soon store data to the specified cache block.

Note: This instruction is a performance hint and may be implemented as a no-op on some implementations.

Affected Registers

None - This instruction does not affect any registers.

For more information on cache management see Section 3.2, "Cache Management Instructions," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic Cache Block Allocation

# Allocate cache block for upcoming stores
lis r3, buffer@ha       # Load high part of buffer address
addi r3, r3, buffer@l   # Complete buffer address
dcba 0, r3              # Allocate cache block at buffer

Prepare Cache for Write Operations

# Allocate cache blocks before filling buffer
li r4, 0                # Initialize offset
li r5, 32               # Cache line size
lis r3, write_buffer@ha # Buffer base address
addi r3, r3, write_buffer@l

# Allocate multiple cache blocks
dcba r3, r4             # Allocate first block
add r4, r4, r5          # Move to next cache line
dcba r3, r4             # Allocate second block

Streaming Write Optimization

# Optimize for streaming write pattern
lis r3, output_array@ha
addi r3, r3, output_array@l
li r4, 0                # Start offset
li r5, 1024             # Total size
li r6, 32               # Cache line size

write_loop:
    dcba r3, r4         # Allocate cache block
    # ... store operations to cache line ...
    add r4, r4, r6      # Next cache line
    cmpw r4, r5         # Check if done
    blt write_loop      # Continue if more to do

Zero Buffer Preparation

# Prepare cache for zeroing large buffer
lis r3, zero_buffer@ha
addi r3, r3, zero_buffer@l
li r4, 0
li r5, 4096             # Buffer size
li r6, 32               # Cache line size

prep_loop:
    dcba r3, r4         # Allocate cache block
    add r4, r4, r6      # Next line
    cmpw r4, r5         # Check bounds
    blt prep_loop

Related Instructions

dcbf, dcbi, dcbst, dcbt, dcbtst, dcbz