Instruction Syntax

Mnemonic	Format	Flags
dcbst	rA,rB	-

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
Reserved	6-10	00000
rA	11-15	Register A (base address)
rB	16-20	Register B (index)
Reserved	21	0
XO	22-30	000110110 (54)
Reserved	31	0

Operation

if rA = 0 then EA ← (rB)
else EA ← (rA) + (rB)

if cache block containing EA is modified then copy to memory

The data cache block store instruction writes the cache block containing the effective address to memory if the block has been modified (is dirty). The cache block remains valid and unmodified after the operation.

Note: This instruction ensures that modified cache data is written to memory without invalidating the cache block.

Affected Registers

None - This instruction does not affect any registers.

For more information on cache management see Section 3.2, "Cache Management Instructions," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic Cache Block Store

# Store a specific cache block to memory
lis r3, data_buffer@ha  # Load high part of buffer address
addi r3, r3, data_buffer@l  # Complete buffer address
dcbst 0, r3             # Store cache block to memory

Store Multiple Cache Blocks

# Store entire buffer to memory while keeping in cache
lis r3, write_buffer@ha
addi r3, r3, write_buffer@l
li r4, 0                # Start offset
li r5, 2048             # Buffer size
li r6, 32               # Cache line size

store_loop:
    dcbst r3, r4        # Store cache block to memory
    add r4, r4, r6      # Next cache line
    cmpw r4, r5         # Check if done
    blt store_loop      # Continue if more blocks
sync                    # Ensure all stores complete

Prepare for DMA Output

# Ensure DMA output buffer is written to memory
lis r3, dma_out_buffer@ha
addi r3, r3, dma_out_buffer@l
li r4, 0
li r5, 4096             # DMA buffer size

dma_store_loop:
    dcbst r3, r4        # Store cache block
    addi r4, r4, 32     # Next cache line (32-byte lines)
    cmpwi r4, r5        # Check bounds
    blt dma_store_loop  # Continue until done
sync                    # Wait for all stores to complete

Coherency Maintenance

# Store modified data before another processor reads it
lis r3, shared_data@ha
addi r3, r3, shared_data@l
stw r4, 0(r3)           # Modify shared data
dcbst 0, r3             # Ensure it's written to memory
sync                    # Synchronize with other processors

Related Instructions

dcba, dcbf, dcbi, dcbt, dcbtst, dcbz, sync