eqv
Equivalent - 7C 00 04 7C
eqv
Instruction Syntax
Mnemonic | Format | Flags |
eqv | rA,rS,rB | Rc = 0 |
eqv. | rA,rS,rB | Rc = 1 |
Instruction Encoding
0
1
1
1
1
1
S
S
S
S
S
A
A
A
A
A
B
B
B
B
B
0
1
0
0
0
1
1
1
0
0
Rc
Field | Bits | Description |
Primary Opcode | 0-5 | 011111 (0x1F) |
rS | 6-10 | Source register S |
rA | 11-15 | Destination register A |
rB | 16-20 | Source register B |
Reserved | 21 | 0 |
XO | 22-30 | 100011100 (284) |
Rc | 31 | Record Condition Register |
Operation
rA ← (rS) ≡ (rB)
The bitwise equivalent of the contents of rS and rB is placed into rA. The equivalent operation is the complement of the exclusive OR operation: bit positions where rS and rB have the same value (both 0 or both 1) result in 1, while bit positions where they differ result in 0.
Note: This instruction performs a bitwise logical equivalence operation on each bit position.
Affected Registers
Condition Register (CR0 field)
(if Rc = 1)
- LT (Less Than)
- GT (Greater Than)
- EQ (Equal)
- SO (Summary Overflow)
For more information on condition codes see Section 2.1.3, "Condition Register," in the PowerPC Microprocessor Family: The Programming Environments manual.
Examples
Basic Equivalence Operation
li r1, 0xAAAA5555 # Load pattern 1010... 0101... li r2, 0x5555AAAA # Load pattern 0101... 1010... eqv r3, r1, r2 # r3 = 0x00000000 (all bits differ) li r4, 0xF0F0F0F0 # Load pattern 1111 0000 repeated li r5, 0xF0F0F0F0 # Load same pattern eqv r6, r4, r5 # r6 = 0xFFFFFFFF (all bits same)
Bit Pattern Comparison
eqv. r3, r1, r2 # Compare bit patterns and set CR0 beq patterns_match # Branch if all bits equivalent (r3 = 0xFFFFFFFF)
Creating Bit Masks
# Create mask where bits are same between two values lwz r1, pattern1(r0) lwz r2, pattern2(r0) eqv r3, r1, r2 # r3 has 1s where r1 and r2 match, 0s where they differ
Data Validation
# Check if received data matches expected pattern lwz r1, received_data(r0) lwz r2, expected_data(r0) eqv r3, r1, r2 # Create equivalence mask cmpwi r3, -1 # Check if all bits are 1 (perfect match) beq data_valid # Branch if data is valid
Error Detection
# Compare two copies of data for errors lwz r1, data_copy1(r0) lwz r2, data_copy2(r0) eqv r3, r1, r2 # Check equivalence cmpwi r3, -1 # All 1s means identical bne data_error # Branch if data differs
Bit Synchronization Check
# Check if control bits are in sync lwz r1, ctrl_reg1(r0) lwz r2, ctrl_reg2(r0) andi. r1, r1, 0x07 # Mask to lower 3 bits andi. r2, r2, 0x07 # Mask to lower 3 bits eqv r3, r1, r2 # Check equivalence andi. r3, r3, 0x07 # Check only masked bits cmpwi r3, 0x07 # Should be all 1s if in sync beq bits_in_sync # Branch if synchronized