iccci
Instruction Cache Coherency Control - 7C 00 07 66
iccci
Instruction Syntax
| Mnemonic | Format | Flags |
| iccci | rA,rB | - |
Instruction Encoding
0
1
1
1
1
1
0
0
0
0
0
A
A
A
A
A
B
B
B
B
B
0
1
1
1
1
0
0
0
1
1
0
| Field | Bits | Description |
| Primary Opcode | 0-5 | 011111 (0x1F) |
| Reserved | 6-10 | 00000 |
| rA | 11-15 | Source register A |
| rB | 16-20 | Source register B |
| Reserved | 21 | 0 |
| XO | 22-30 | 1111000110 (966) |
| Reserved | 31 | 0 |
Operation
if rA = 0 then EA ← 0 else EA ← (rA) EA ← EA + (rB) Invalidate all instruction cache blocks that hit on EA
The instruction cache coherency control instruction is used to maintain coherency between instruction caches in multiprocessor systems. It invalidates all instruction cache blocks that hit on the effective address in all processors in the coherency domain.
Note: This is a privileged instruction typically used by operating system and hypervisor code for multiprocessor cache coherency. The instruction may cause a system alignment interrupt if the effective address is not properly aligned. This instruction is implementation-specific and may not be available on all PowerPC processors.
Affected Registers
None - This instruction does not affect any registers.
For more information on cache coherency see Section 2.1.1, "Cache Model," in the PowerPC Microprocessor Family: The Programming Environments manual.
Examples
Multiprocessor Code Modification
# Invalidate instruction cache across all processors lis r3, shared_code@ha addi r3, r3, shared_code@l # Modify shared code lis r4, new_instruction@ha addi r4, r4, new_instruction@l lwz r5, 0(r4) # Load new instruction stw r5, 0(r3) # Store to shared code area # Ensure coherency across all processors dcbst 0, r3 # Flush data cache to memory sync # Ensure store completes iccci 0, r3 # Invalidate instruction cache on all processors isync # Synchronize instruction prefetch
Operating System Module Loading
# Load kernel module and ensure instruction cache coherency
lis r3, module_base@ha
addi r3, r3, module_base@l
lwz r4, module_size(r0) # Load module size
li r5, 0 # Current offset
li r6, 32 # Cache line size
# Flush entire module from all instruction caches
module_coherency_loop:
add r7, r3, r5 # Current address
dcbst 0, r7 # Flush data cache
iccci 0, r7 # Invalidate instruction cache on all CPUs
add r5, r5, r6 # Next cache line
cmpw r5, r4 # Check if done
blt module_coherency_loop
sync # Ensure all operations complete
isync # Synchronize instruction stream
Hypervisor Guest Code Patching
# Patch guest code and maintain coherency across virtual CPUs
lis r3, guest_code_page@ha
addi r3, r3, guest_code_page@l
# Apply security patch to guest code
lis r4, security_patch@ha
addi r4, r4, security_patch@l
lwz r5, patch_size(r0)
li r6, 0
apply_patch_loop:
lwzx r7, r4, r6 # Load patch byte
stwx r7, r3, r6 # Apply to guest code
addi r6, r6, 4 # Next word
cmpw r6, r5 # Check if done
blt apply_patch_loop
# Ensure coherency across all virtual CPUs
li r6, 0
coherency_loop:
add r7, r3, r6 # Current address
dcbst 0, r7 # Flush data cache
iccci 0, r7 # Invalidate instruction cache globally
addi r6, r6, 32 # Next cache line
cmpw r6, r5 # Check if done
blt coherency_loop
sync # Memory barrier
isync # Instruction synchronization
Distributed Debugging System
# Install breakpoints across all processors in debug session
lis r3, breakpoint_list@ha
addi r3, r3, breakpoint_list@l
lwz r4, num_breakpoints(r0)
li r5, 0
install_breakpoints:
lwzx r6, r3, r5 # Load breakpoint address
# Save original instruction
lwz r7, 0(r6) # Load original instruction
stwx r7, r3, r5 # Save in parallel array
# Install breakpoint instruction
lis r8, 0x7FE0 # Breakpoint instruction
ori r8, r8, 0x0008
stw r8, 0(r6) # Install breakpoint
# Ensure coherency across all debug targets
dcbst 0, r6 # Flush data cache
iccci 0, r6 # Invalidate instruction cache on all CPUs
addi r5, r5, 4 # Next breakpoint
subi r4, r4, 1 # Decrement counter
cmpwi r4, 0
bne install_breakpoints
sync # Ensure all modifications visible
isync # Synchronize instruction stream
Real-Time System Critical Section Update
# Update real-time critical section code across all processors
lis r3, critical_section@ha
addi r3, r3, critical_section@l
# Disable interrupts on all processors first
lis r4, disable_interrupts@ha
addi r4, r4, disable_interrupts@l
mtctr r4
bctrl # Call interrupt disable routine
# Update critical section code
lis r5, new_critical_code@ha
addi r5, r5, new_critical_code@l
lwz r6, critical_size(r0)
li r7, 0
update_critical_loop:
lwzx r8, r5, r7 # Load new code
stwx r8, r3, r7 # Store to critical section
addi r7, r7, 4 # Next word
cmpw r7, r6 # Check if done
blt update_critical_loop
# Ensure coherency across all real-time processors
li r7, 0
critical_coherency_loop:
add r8, r3, r7 # Current address
dcbst 0, r8 # Flush data cache
iccci 0, r8 # Invalidate instruction cache globally
addi r7, r7, 32 # Next cache line
cmpw r7, r6 # Check if done
blt critical_coherency_loop
sync # Memory barrier
isync # Instruction synchronization
# Re-enable interrupts
lis r4, enable_interrupts@ha
addi r4, r4, enable_interrupts@l
mtctr r4
bctrl # Call interrupt enable routine
Firmware Update Across Processor Complex
# Update firmware and maintain coherency across processor complex
lis r3, firmware_base@ha
addi r3, r3, firmware_base@l
lis r4, new_firmware@ha
addi r4, r4, new_firmware@l
lwz r5, firmware_size(r0)
# Copy new firmware
li r6, 0
firmware_copy_loop:
lwzx r7, r4, r6 # Load from new firmware
stwx r7, r3, r6 # Store to firmware area
addi r6, r6, 4 # Next word
cmpw r6, r5 # Check if done
blt firmware_copy_loop
# Invalidate instruction caches across entire processor complex
li r6, 0
firmware_coherency_loop:
add r7, r3, r6 # Current firmware address
dcbst 0, r7 # Flush data cache
iccci 0, r7 # Invalidate instruction cache on all processors
addi r6, r6, 32 # Next cache line
cmpw r6, r5 # Check if done
blt firmware_coherency_loop
sync # Ensure all cache operations complete
isync # Synchronize instruction prefetch
# Signal firmware update complete to all processors
lis r7, update_complete_flag@ha
addi r7, r7, update_complete_flag@l
li r8, 1
stw r8, 0(r7) # Set completion flag
dcbst 0, r7 # Ensure flag is visible to all processors
Cluster Computing Task Distribution
# Distribute computational tasks across cluster nodes
lis r3, task_code_buffer@ha
addi r3, r3, task_code_buffer@l
lis r4, task_template@ha
addi r4, r4, task_template@l
lwz r5, task_size(r0)
# Customize task code for each node
lwz r6, node_count(r0)
li r7, 0 # Node index
distribute_tasks:
# Calculate task code address for this node
mullw r8, r7, r5 # Offset for this node
add r9, r3, r8 # Task code address for node
# Copy and customize task template
li r10, 0
copy_task_loop:
lwzx r11, r4, r10 # Load from template
# Customize instruction for node (simplified)
add r11, r11, r7 # Add node ID to instruction
stwx r11, r9, r10 # Store customized instruction
addi r10, r10, 4 # Next word
cmpw r10, r5 # Check if done
blt copy_task_loop
# Ensure coherency for this node's task code
li r10, 0
node_coherency_loop:
add r11, r9, r10 # Current address
dcbst 0, r11 # Flush data cache
iccci 0, r11 # Invalidate instruction cache cluster-wide
addi r10, r10, 32 # Next cache line
cmpw r10, r5 # Check if done
blt node_coherency_loop
addi r7, r7, 1 # Next node
cmpw r7, r6 # Check if all nodes done
blt distribute_tasks
sync # Ensure all cache operations complete
isync # Synchronize instruction stream
Dynamic Load Balancing Code Migration
# Migrate hot code between processors for load balancing
lis r3, hot_function@ha
addi r3, r3, hot_function@l
lwz r4, function_size(r0)
lis r5, target_processor_cache@ha
addi r5, r5, target_processor_cache@l
# Copy function to target processor's local cache
li r6, 0
migrate_function_loop:
lwzx r7, r3, r6 # Load from source
stwx r7, r5, r6 # Store to target cache
addi r6, r6, 4 # Next word
cmpw r6, r4 # Check if done
blt migrate_function_loop
# Invalidate old function location on all processors
li r6, 0
invalidate_old_loop:
add r7, r3, r6 # Old function address
iccci 0, r7 # Invalidate on all processors
addi r6, r6, 32 # Next cache line
cmpw r6, r4 # Check if done
blt invalidate_old_loop
# Ensure new function is coherent across all processors
li r6, 0
coherent_new_loop:
add r7, r5, r6 # New function address
dcbst 0, r7 # Flush data cache
iccci 0, r7 # Invalidate instruction cache globally
addi r6, r6, 32 # Next cache line
cmpw r6, r4 # Check if done
blt coherent_new_loop
sync # Memory barrier
isync # Instruction synchronization
# Update function pointer to new location
lis r8, function_pointer@ha
addi r8, r8, function_pointer@l
stw r5, 0(r8) # Update pointer
dcbst 0, r8 # Ensure pointer update is visible
Security Policy Enforcement Update
# Update security enforcement code across all processors
lis r3, security_check_routine@ha
addi r3, r3, security_check_routine@l
lis r4, updated_security_code@ha
addi r4, r4, updated_security_code@l
lwz r5, security_code_size(r0)
# Atomically update security checking code
li r6, 0
update_security_loop:
lwzx r7, r4, r6 # Load updated security code
stwx r7, r3, r6 # Store to security routine
addi r6, r6, 4 # Next word
cmpw r6, r5 # Check if done
blt update_security_loop
# Ensure security update is coherent across all processors
li r6, 0
security_coherency_loop:
add r7, r3, r6 # Security routine address
dcbst 0, r7 # Flush data cache
iccci 0, r7 # Invalidate instruction cache on all processors
addi r6, r6, 32 # Next cache line
cmpw r6, r5 # Check if done
blt security_coherency_loop
sync # Ensure all updates complete
isync # Synchronize instruction stream
# Notify all processors that security update is complete
lis r8, security_update_flag@ha
addi r8, r8, security_update_flag@l
li r9, 1
stw r9, 0(r8) # Set update complete flag
dcbst 0, r8 # Ensure flag is visible to all processors