lswi
Load String Word Immediate - 7C 00 00 4A
lswi

Instruction Syntax

Mnemonic Format Flags
lswi rD,rA,NB None

Instruction Encoding

0
1
1
1
1
1
D
D
D
D
D
A
A
A
A
A
N
N
N
N
N
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0

Field Bits Description
Primary Opcode 0-5 011111 (0x1F)
rD 6-10 Starting destination register
rA 11-15 Base register (can be 0)
NB 16-20 Number of bytes to load (0-31)
XO 21-30 0000000001 (1) - Extended opcode
Rc 31 Record bit (0)

Operation

if rA = 0 then EA ← 0
else EA ← (rA)
n ← NB
if n = 0 then n ← 32
for i = 0 to n-1
    if i < 4 then
        GPR[rD + i] ← MEM(EA + i*4, 4)
    else
        GPR[((rD + i) mod 32)] ← MEM(EA + i*4, 4)

Words are loaded from consecutive memory locations starting at the effective address. The effective address is the contents of register rA, or zero if rA is 0. The number of words loaded is determined by the NB field: if NB is 0, 32 words are loaded; otherwise, NB words are loaded.

Note: This instruction provides flexible bulk loading with an immediate count. The destination registers wrap around if more than 32 registers would be needed. This instruction is particularly useful for loading variable-length data structures or when the exact number of words to load is known at assembly time.

Affected Registers

Examples

Example 1: Load specific number of words

# Load 8 words starting from r3
lswi r3, r1, 8      # Load 8 words from address in r1

Example 2: Load all 32 words

# Load all 32 words (NB = 0)
lswi r0, r2, 0      # Load r0-r31 from address in r2

Example 3: Load with register wrapping

# Load 16 words starting from r20
lswi r20, r4, 16    # Load r20-r31, then r0-r3

Related Instructions

lswx, stswi, stswx, lmw

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