Instruction Syntax

Mnemonic	Format	Flags
lswx	rD,rA,rB	None

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rD	6-10	Starting destination register
rA	11-15	Base register (can be 0)
rB	16-20	Index register (also provides count)
XO	21-30	0000000001 (1) - Extended opcode
Rc	31	Record bit (0)

Operation

if rA = 0 then EA ← (rB)
else EA ← (rA) + (rB)
n ← (rB)[27:31]  # Low-order 5 bits of rB
if n = 0 then n ← 32
for i = 0 to n-1
    if i < 4 then
        GPR[rD + i] ← MEM(EA + i*4, 4)
    else
        GPR[((rD + i) mod 32)] ← MEM(EA + i*4, 4)

Words are loaded from consecutive memory locations starting at the effective address. The effective address is computed by adding the contents of registers rA and rB, or just rB if rA is 0. The number of words loaded is determined by the low-order 5 bits of register rB: if these bits are 0, 32 words are loaded; otherwise, that many words are loaded.

Note: This instruction provides flexible bulk loading with a dynamic count from a register. The destination registers wrap around if more than 32 registers would be needed. This instruction is particularly useful for loading variable-length data structures when the count is computed at runtime.

Affected Registers

• rD through rD+n-1: Loaded with consecutive words from memory (wrapping around if needed)
• rA: Used as base register (if not 0)
• rB: Used as index register and provides count

Examples

Example 1: Load with dynamic count

# Load count from r4, base address in r3
li r4, 8           # Set count to 8
lswx r5, r3, r4    # Load 8 words starting from r5

Example 2: Load all 32 words

# Load all 32 words (count = 0)
li r4, 0           # Set count to 0 (loads 32 words)
lswx r0, r3, r4    # Load r0-r31 from address in r3

Example 3: Load with computed address

# Load with computed address and count
add r4, r1, r2     # Compute address: r1 + r2
li r5, 16          # Set count to 16
lswx r6, r4, r5    # Load 16 words starting from r6

Related Instructions

lswi, stswi, stswx, lmw