Instruction Syntax

Mnemonic	Format	Flags
mtmsr	rS	None

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rS	6-10	Source register
Reserved	11-20	Should be zero
XO	21-30	0x1A4 (420) - Extended opcode
Reserved	31	Should be zero

Operation

MSR ← rS

The contents of general-purpose register rS are copied to the Machine State Register (MSR).

Note: The mtmsr instruction provides access to the processor state for system software. The MSR contains critical system information such as privilege level, interrupt enable status, and other control bits that determine processor behavior.

Affected Registers

Machine State Register (MSR)

(always)

• MSR - Loaded with complete contents from rS

General Purpose Register (GPR)

(read only)

• rS - Source register (read only)

For more information on machine state see Section 2.1.2, "Machine State Register (MSR)," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic MSR Write

# Write to machine state register
mtmsr r3                # Copy r3 to MSR
# Processor state now reflects r3 contents

Enable Interrupts

# Enable external interrupts
mfmsr r4                # Get current MSR
ori r5, r4, 0x8000     # Set EE bit (bit 15)
mtmsr r5                # Update MSR
# External interrupts now enabled

Disable Interrupts

# Disable external interrupts
mfmsr r6                # Get current MSR
andi. r7, r6, ~0x8000  # Clear EE bit (bit 15)
mtmsr r7                # Update MSR
# External interrupts now disabled

Change Privilege Level

# Switch to user mode
mfmsr r8                # Get current MSR
ori r9, r8, 0x1000     # Set PR bit (bit 16)
mtmsr r9                # Switch to user mode
# Now running in user mode

Related Instructions

mfmsr, mtspr, mfspr