Instruction Syntax

Mnemonic	Format	Flags
mfmsr	rD	None

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rD	6-10	Destination register
Reserved	11-20	Should be zero
XO	21-30	0x0A6 (166) - Extended opcode
Reserved	31	Should be zero

Operation

rD ← MSR

The entire contents of the Machine State Register (MSR) are copied to general-purpose register rD. The MSR contains 32 bits representing the current processor state including privilege level, interrupt enable status, and other system control bits.

Note: This instruction provides access to the current processor state for system software. The MSR contains critical system information such as privilege level, interrupt enable status, and other control bits that determine processor behavior.

Affected Registers

General Purpose Register

(always)

• rD - Loaded with complete MSR contents

Machine State Register (MSR)

(read only)

• MSR - Source register (read only)

For more information on machine state see Section 2.1.2, "Machine State Register (MSR)," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic MSR Read

# Read current machine state
mfmsr r3                # Copy MSR to r3
# r3 now contains current processor state

Check Privilege Level

# Check if running in supervisor mode
mfmsr r4                # Get current MSR
andi. r5, r4, 0x1000   # Check PR bit (bit 16)
beq supervisor_mode     # Branch if in supervisor mode
# Running in user mode

Check Interrupt Status

# Check if interrupts are enabled
mfmsr r6                # Get current MSR
andi. r7, r6, 0x8000   # Check EE bit (bit 15)
bne interrupts_enabled  # Branch if interrupts enabled
# Interrupts are disabled

Save Processor State

# Save current processor state
mfmsr r8                # Save MSR
# ... perform operations that might change state ...
mtmsr r8                # Restore original state

Context Switching

# Save processor context
mfmsr r10               # Save MSR
# ... save other registers ...

bl context_switch       # Switch to different context

# Restore processor context
mtmsr r10               # Restore MSR
# ... restore other registers ...

Interrupt Handler

# Interrupt handler entry
interrupt_handler:
    mfmsr r12           # Save MSR
    # ... handle interrupt ...
    mtmsr r12           # Restore MSR
    rfi                 # Return from interrupt

System Call Handler

# System call entry point
system_call:
    mfmsr r14           # Save current MSR
    # Switch to supervisor mode if needed
    ori r15, r14, 0x1000 # Set PR bit for supervisor mode
    mtmsr r15           # Update MSR
    
    # ... handle system call ...
    
    mtmsr r14           # Restore original MSR
    rfi                 # Return to user mode

Debugging System State

# Debug processor state
debug_point:
    mfmsr r16           # Save MSR for debugging
    # ... perform operations ...
    
    # Debug: check if MSR changed unexpectedly
    mfmsr r17           # Get current MSR
    cmpw r16, r17       # Compare saved vs current
    beq state_ok        # Branch if unchanged
    # Handle unexpected state change

Check Floating-Point Status

# Check if floating-point is enabled
mfmsr r18               # Get current MSR
andi. r19, r18, 0x2000 # Check FP bit (bit 13)
bne fp_enabled          # Branch if floating-point enabled
# Floating-point is disabled

System Initialization

# System initialization sequence
system_init:
    mfmsr r20           # Get current MSR
    # Set up desired processor state
    li r21, 0x8000      # Enable interrupts (EE bit)
    or r22, r20, r21    # Combine with current state
    mtmsr r22           # Update MSR
    
    # Continue with system initialization

Related Instructions

mtmsr, rfi, sc