Instruction Syntax

Mnemonic	Format	Flags
rfi	None	None

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	010011 (0x13)
Reserved	6-10	00000
Reserved	11-15	00000
Reserved	16-20	00000
Reserved	21-29	000000000
XO	30-31	100 (Extended opcode)

Operation

MSR ← SRR1
PC ← SRR0
Refetch and execute instructions following rfi

The Machine State Register (MSR) is restored from SRR1, and the Program Counter (PC) is restored from SRR0. The processor then refetches and executes instructions following the rfi instruction.

Note: The rfi instruction is used to return from an interrupt or exception handler. It restores the processor state that was saved when the interrupt occurred.

Affected Registers

Machine State Register (MSR)

• All MSR fields are restored from SRR1

Program Counter (PC)

• PC is restored from SRR0

Special Purpose Registers (SPRs)

• SRR0 (Saved Return Register 0)
• SRR1 (Saved Return Register 1)

Examples

Basic Interrupt Return

# Interrupt handler
interrupt_handler:
    # Process interrupt
    # ...
    rfi                 # Return from interrupt

Exception Handler

# Exception handler
exception_handler:
    # Save registers
    stwu r1, -16(r1)
    stw r3, 4(r1)
    stw r4, 8(r1)
    
    # Handle exception
    # ...
    
    # Restore registers
    lwz r4, 8(r1)
    lwz r3, 4(r1)
    addi r1, r1, 16
    
    rfi                 # Return from exception

System Call Return

# System call handler
syscall_handler:
    # Process system call
    # ...
    rfi                 # Return to user mode

Related Instructions

sc, rfsvc, mtmsr, mfmsr