Instruction Syntax

Mnemonic	Format	Flags
mulhw	rD,rA,rB	OE = 0, Rc = 0
mulhw.	rD,rA,rB	OE = 0, Rc = 1
mulhwo	rD,rA,rB	OE = 1, Rc = 0
mulhwo.	rD,rA,rB	OE = 1, Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rD	6-10	Destination register
rA	11-15	Source register A
rB	16-20	Source register B
OE	21	Overflow Exception
XO	22-29	150 (Extended opcode)
Rc	30-31	Record Condition Register

Operation

rD ← (rA × rB)[32:63]

The contents of registers rA and rB are multiplied as signed 32-bit integers, and the high-order 32 bits of the 64-bit result are placed into rD.

Note: The mulhw instruction performs signed multiplication and returns the high-order word of the result. This is useful for extended precision arithmetic and division algorithms.

Affected Registers

Condition Register (CR0 field)

(if Rc = 1)

• LT (Less Than)
• GT (Greater Than)
• EQ (Equal)
• SO (Summary Overflow)

Note: CR0 field reflects the sign of the high-order word result.

XER (Exception Register)

(if OE = 1)

• SO (Summary Overflow)
• OV (Overflow)

For more information on condition codes see Section 2.1.3, "Condition Register," and Section 2.1.5, "XER Register," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic High Word Multiplication

mulhw r3, r1, r2     # r3 = high 32 bits of (r1 * r2)
mulhw. r3, r1, r2    # Same as above, but also sets condition register

Extended Precision Arithmetic

# Calculate high word of 64-bit multiplication
lwz r4, 0(r10)       # Load first operand
lwz r5, 4(r10)       # Load second operand  
mulhw r6, r4, r5     # Get high word of product

Division Algorithm Support

# Part of division algorithm using high word
mulhw r7, r8, r9     # Get high word for division step
# Use result in subsequent division operations

Overflow Detection

mulhwo r3, r1, r2    # Multiply with overflow exception enabled
# If overflow occurs, an exception is raised

Related Instructions

mulhwu, mulli, mullw