Instruction Syntax

Mnemonic	Format	Flags
mulli	rD,rA,SIMM	None

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	000111 (0x07)
rD	6-10	Destination register
rA	11-15	Source register A
SIMM	16-31	16-bit signed immediate

Operation

rD ← (rA × SIMM)[32:63]

The contents of register rA are multiplied by the signed immediate value SIMM, and the low-order 32 bits of the result are placed into rD.

Note: The mulli instruction performs signed multiplication with an immediate operand and returns the low-order word of the result. This is useful for quick multiplication by small constants.

Affected Registers

General Purpose Registers (GPRs)

(always)

• rD - Destination register (loaded with low-order 32 bits of product)

General Purpose Registers (GPRs)

(read only)

• rA - Source register (read only)

Examples

Basic Immediate Multiplication

mulli r3, r1, 5        # r3 = r1 * 5
mulli r4, r2, -10      # r4 = r2 * (-10)

Array Index Calculation

# Calculate array index: index * sizeof(element)
mulli r5, r6, 4        # r5 = r6 * 4 (for 32-bit elements)
add r7, r8, r5         # r7 = base_address + offset

Constant Scaling

# Scale a value by a constant factor
lwz r9, 0(r10)         # Load value
mulli r11, r9, 100     # Scale by 100
# r11 now contains scaled value

Address Calculation

# Calculate address offset for structure member
mulli r12, r13, 16     # r12 = r13 * 16 (structure size)
add r14, r15, r12      # r14 = base + offset

Related Instructions

mulhw, mulhwu, mullw