srw
Shift Right Word - 7C 00 00 34
srw
Instruction Syntax
| Mnemonic | Format | Flags |
| srw | rA,rS,rB | Rc = 0 |
| srw. | rA,rS,rB | Rc = 1 |
Instruction Encoding
0
1
1
1
1
1
S
S
S
S
S
A
A
A
A
A
B
B
B
B
B
0
0
0
0
0
0
0
0
0
Rc
| Field | Bits | Description |
| Primary Opcode | 0-5 | 011111 (0x1F) |
| rS | 6-10 | Source register |
| rA | 11-15 | Destination register |
| rB | 16-20 | Shift amount register (low-order 6 bits) |
| Reserved | 21-29 | 000000000 |
| Rc | 30-31 | Record Condition Register |
Operation
rA ← (rS) >> (rB)[26:31] (logical)
The source value (rS) is logically shifted right by the number of positions specified by the low-order 6 bits of (rB). The result is placed into rA.
Note: Logical shift fills with zeros. If the shift amount is 32 or greater, the result is 0.
Affected Registers
General Purpose Registers (GPRs)
- rA (Destination register)
Condition Register (CR0 field)
(if Rc = 1)
- LT (Less Than)
- GT (Greater Than)
- EQ (Equal)
- SO (Summary Overflow)
Examples
Basic Logical Right Shift
# Shift r1 right by amount in r2 (logical) srw r3, r1, r2 # r3 = r1 >> (r2 & 0x3F) (logical) srw. r3, r1, r2 # Same as above, but also sets condition register
Division by Power of 2 (Unsigned)
# Divide r1 by 2^r2 (unsigned) srw r3, r1, r2 # r3 = r1 / 2^(r2 & 0x3F) (unsigned)
Bit Field Extraction
# Extract bits 8-15 from r1 li r2, 8 # Shift amount srw r3, r1, r2 # r3 = (r1 >> 8) & 0xFF