Instruction Syntax

Mnemonic	Format	Flags
sraw	rA,rS,rB	Rc = 0
sraw.	rA,rS,rB	Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rS	6-10	Source register
rA	11-15	Destination register
rB	16-20	Shift amount register (low-order 6 bits)
Reserved	21-29	000000000
Rc	30-31	Record Condition Register

Operation

rA ← (rS) >> (rB)[26:31] (arithmetic)
XER[CA] ← ((rS) >> ((rB)[26:31] - 1)) & 1

The source value (rS) is arithmetically shifted right by the number of positions specified by the low-order 6 bits of (rB). The result is placed into rA. The carry bit is set if any 1 bits were shifted out.

Note: Arithmetic shift preserves the sign bit. If the shift amount is 32 or greater, the result is 0 or -1 depending on the sign of the source.

Affected Registers

General Purpose Registers (GPRs)

• rA (Destination register)

XER (Exception Register)

• CA (Carry) - Set if any 1 bits were shifted out

Condition Register (CR0 field)

(if Rc = 1)

• LT (Less Than)
• GT (Greater Than)
• EQ (Equal)
• SO (Summary Overflow)

Examples

Basic Arithmetic Right Shift

# Shift r1 right by amount in r2 (arithmetic)
sraw r3, r1, r2     # r3 = r1 >> (r2 & 0x3F) (arithmetic)
sraw. r3, r1, r2    # Same as above, but also sets condition register

Division by Power of 2

# Divide r1 by 2^r2 (arithmetic)
sraw r3, r1, r2     # r3 = r1 / 2^(r2 & 0x3F) (arithmetic)

Sign Extension

# Sign extend a 16-bit value in r1
sraw r2, r1, 16     # r2 = r1 >> 16 (arithmetic)

Related Instructions

srawi, srw, slw, rlwinm