srawi
Shift Right Algebraic Word Immediate - 7C 00 00 66
srawi
Instruction Syntax
| Mnemonic | Format | Flags |
| srawi | rA,rS,SH | Rc = 0 |
| srawi. | rA,rS,SH | Rc = 1 |
Instruction Encoding
0
1
1
1
1
1
S
S
S
S
S
A
A
A
A
A
H
H
H
H
H
0
0
0
0
0
0
0
0
0
Rc
| Field | Bits | Description |
| Primary Opcode | 0-5 | 011111 (0x1F) |
| rS | 6-10 | Source register |
| rA | 11-15 | Destination register |
| SH | 16-20 | Shift amount (0-31) |
| Reserved | 21-29 | 000000000 |
| Rc | 30-31 | Record Condition Register |
Operation
rA ← (rS) >> SH (arithmetic) XER[CA] ← ((rS) >> (SH - 1)) & 1
The source value (rS) is arithmetically shifted right by SH positions. The result is placed into rA. The carry bit is set if any 1 bits were shifted out.
Note: Arithmetic shift preserves the sign bit. If SH is 32 or greater, the result is 0 or -1 depending on the sign of the source.
Affected Registers
General Purpose Registers (GPRs)
- rA (Destination register)
XER (Exception Register)
- CA (Carry) - Set if any 1 bits were shifted out
Condition Register (CR0 field)
(if Rc = 1)
- LT (Less Than)
- GT (Greater Than)
- EQ (Equal)
- SO (Summary Overflow)
Examples
Basic Arithmetic Right Shift
# Shift r1 right by 4 positions (arithmetic) srawi r2, r1, 4 # r2 = r1 >> 4 (arithmetic) srawi. r2, r1, 4 # Same as above, but also sets condition register
Division by Power of 2
# Divide r1 by 16 (arithmetic) srawi r2, r1, 4 # r2 = r1 / 16 (arithmetic)
Sign Extension
# Sign extend a 16-bit value in r1 srawi r2, r1, 16 # r2 = r1 >> 16 (arithmetic)