Instruction Syntax

Mnemonic	Format	Flags
stfsu	frS,d(rA)	None

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	110101 (0x35)
frS	6-10	Source floating-point register
rA	11-15	Base register (updated)
SIMM	16-31	Signed immediate offset

Operation

EA ← (rA) + SIMM
(EA) ← (frS)[32:63]
rA ← EA

The effective address is calculated by adding the signed immediate offset to the base register. The single-precision floating-point value (high-order 32 bits) of the source register is stored at the effective address. The base register is updated with the effective address.

Note: The stfsu instruction stores a 32-bit single-precision floating-point value to memory and updates the base register with the effective address. The address must be aligned to a 4-byte boundary.

Affected Registers

General Purpose Registers (GPRs)

• rA (Base register) - Updated with effective address

Memory

• Single-precision floating-point value at effective address (EA)

Examples

Basic Store Floating-Point Single with Update

# Store single-precision value and update base register
stfsu fr1, 4(r3)    # Store at r3 + 4, then r3 = r3 + 4

Array of Singles with Auto-Increment

# Store singles in array sequentially
li r3, array        # Load array base address
li r4, 0            # Counter
loop:
stfsu fr1, 4(r3)    # Store single, increment address by 4
addi r4, r4, 1      # Increment counter
cmpwi r4, 10        # Check if done
blt loop

Floating-Point Data Processing

# Process floating-point data with auto-increment
li r3, data_buffer  # Load data buffer address
li r4, 0            # Counter
process_loop:
fadds fr2, fr0, fr1 # Calculate result (single precision)
stfsu fr2, 4(r3)    # Store result, increment address
addi r4, r4, 1      # Increment counter
cmpwi r4, 100       # Check if done
blt process_loop

Related Instructions

stfs, stfsux, stfsx, lfsu