Instruction Syntax

Mnemonic	Format	Flags
stfsux	frS,rA,rB	None

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
frS	6-10	Source floating-point register
rA	11-15	Base register (updated)
rB	16-20	Index register
Reserved	21-29	000000000
Reserved	30-31	00

Operation

EA ← (rA) + (rB)
(EA) ← (frS)[32:63]
rA ← EA

The effective address is calculated by adding the base register to the index register. The single-precision floating-point value (high-order 32 bits) of the source register is stored at the effective address. The base register is updated with the effective address.

Note: The stfsux instruction stores a 32-bit single-precision floating-point value to memory and updates the base register with the effective address. The address must be aligned to a 4-byte boundary.

Affected Registers

General Purpose Registers (GPRs)

• rA (Base register) - Updated with effective address

Memory

• Single-precision floating-point value at effective address (EA)

Examples

Basic Store Floating-Point Single with Update Indexed

# Store single-precision value using indexed addressing with update
stfsux fr1, r3, r4   # Store fr1 at r3 + r4, then r3 = r3 + r4

Array of Singles with Dynamic Index

# Store singles in array using dynamic index
li r3, array         # Load array base address
li r4, 0             # Index = 0
stfsux fr1, r3, r4   # Store single, update base address

Floating-Point Data Processing

# Process floating-point data with dynamic addressing
li r3, data_buffer   # Load data buffer address
li r4, 0             # Index = 0
process_loop:
fadds fr2, fr0, fr1  # Calculate result (single precision)
stfsux fr2, r3, r4   # Store result, update base address
addi r4, r4, 4       # Increment index by 4 bytes
cmpwi r4, 400        # Check if done (100 singles * 4 bytes)
blt process_loop

Related Instructions

stfs, stfsu, stfsx, lfsux