Instruction Syntax

Mnemonic	Format	Flags
sthu	rS,d(rA)	None

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	101101 (0x2D)
rS	6-10	Source register
rA	11-15	Base register (updated)
SIMM	16-31	Signed immediate offset

Operation

EA ← (rA) + SIMM
(EA) ← (rS)[16:31]
rA ← EA

The effective address is calculated by adding the signed immediate offset to the base register. The least significant halfword (bits 16-31) of the source register is stored at the effective address. The base register is updated with the effective address.

Note: The sthu instruction stores a 16-bit halfword to memory and updates the base register with the effective address. The address must be aligned to a 2-byte boundary.

Affected Registers

General Purpose Registers (GPRs)

• rA (Base register) - Updated with effective address

Memory

• Halfword at effective address (EA)

Examples

Basic Store Halfword with Update

# Store halfword and update base register
sthu r1, 2(r3)    # Store at r3 + 2, then r3 = r3 + 2

Array of Halfwords with Auto-Increment

# Store halfwords in array sequentially
li r3, array        # Load array base address
li r4, 0            # Counter
loop:
sthu r1, 2(r3)      # Store halfword, increment address by 2
addi r4, r4, 1      # Increment counter
cmpwi r4, 10        # Check if done
blt loop

Data Processing with Auto-Increment

# Process data with auto-increment
li r3, data_buffer  # Load data buffer address
li r4, 0            # Counter
process_loop:
add r5, r6, r7      # Calculate value
sthu r5, 2(r3)      # Store halfword, increment address
addi r4, r4, 1      # Increment counter
cmpwi r4, 100       # Check if done
blt process_loop

Related Instructions

sth, sthux, sthx, lhu