sthx
Store Halfword Indexed - 7C 00 00 1D
sthx
Instruction Syntax
| Mnemonic | Format | Flags |
| sthx | rS,rA,rB | None |
Instruction Encoding
0
1
1
1
1
1
S
S
S
S
S
A
A
A
A
A
B
B
B
B
B
0
0
0
0
0
0
0
0
0
0
0
| Field | Bits | Description |
| Primary Opcode | 0-5 | 011111 (0x1F) |
| rS | 6-10 | Source register |
| rA | 11-15 | Base register |
| rB | 16-20 | Index register |
| Reserved | 21-29 | 000000000 |
| Reserved | 30-31 | 00 |
Operation
EA ← (rA) + (rB) (EA) ← (rS)[16:31]
The effective address is calculated by adding the base register to the index register. The least significant halfword (bits 16-31) of the source register is stored at the effective address.
Note: The sthx instruction stores a 16-bit halfword to memory using indexed addressing. The address must be aligned to a 2-byte boundary.
Affected Registers
Memory
- Halfword at effective address (EA)
Examples
Basic Store Halfword Indexed
# Store halfword using indexed addressing sthx r1, r3, r4 # Store r1 at address r3 + r4
Array of Halfwords with Dynamic Index
# Store halfword in array using dynamic index li r3, array # Load array base address li r4, 4 # Index = 4 (2 * 2 bytes) sthx r1, r3, r4 # Store halfword at array[2]
Dynamic Addressing
# Store halfword using dynamic index calculation li r3, base_addr # Load base address add r4, r5, r6 # Calculate index dynamically sthx r1, r3, r4 # Store halfword at base_addr + index