rlwnm
Rotate Left Word then AND with Mask - 5C 00 00 00
rlwnm
Instruction Syntax
| Mnemonic | Format | Flags |
| rlwnm | rA,rS,rB,MB,ME | Rc = 0 |
| rlwnm. | rA,rS,rB,MB,ME | Rc = 1 |
Instruction Encoding
0
1
0
1
1
1
S
S
S
S
S
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
E
E
E
E
E
Rc
| Field | Bits | Description |
| Primary Opcode | 0-5 | 010111 (0x17) |
| rS | 6-10 | Source register |
| rA | 11-15 | Destination register |
| rB | 16-20 | Shift amount register (low-order 5 bits) |
| MB | 21-25 | Mask begin bit (0-31) |
| ME | 26-30 | Mask end bit (0-31) |
| Rc | 31 | Record Condition Register |
Operation
rA ← ROTATE((rS), (rB)[27:31]) & MASK
The source value (rS) is rotated left by the low-order 5 bits of (rB), then ANDed with MASK (bits MB to ME). The result is placed into rA.
Note: MASK is a field mask where bits MB through ME are set to 1, and all other bits are 0. The shift amount is taken from the low-order 5 bits of rB.
Affected Registers
General Purpose Registers (GPRs)
- rA (Destination register)
Condition Register (CR0 field)
(if Rc = 1)
- LT (Less Than)
- GT (Greater Than)
- EQ (Equal)
- SO (Summary Overflow)
Examples
Basic Rotation and Masking
# Rotate r1 left by amount in r2 and mask bits 16-23 rlwnm r3, r1, r2, 16, 23
Dynamic Field Extraction
# Extract field starting at bit position in r2 rlwnm r3, r1, r2, 0, 7
Variable Shift and Mask
# Shift r1 by amount in r2 and mask to 8 bits rlwnm r3, r1, r2, 24, 31