add
Add - 7C 00 02 14
add
Instruction Syntax
| Mnemonic | Format | Flags |
| add | rD,rA,rB | OE = 0, Rc = 0 |
| add. | rD,rA,rB | OE = 0, Rc = 1 |
| addo | rD,rA,rB | OE = 1, Rc = 0 |
| addo. | rD,rA,rB | OE = 1, Rc = 1 |
Instruction Encoding
0
1
1
1
1
1
D
D
D
D
D
A
A
A
A
A
B
B
B
B
B
OE
1
0
0
0
0
1
0
1
0
Rc
| Field | Bits | Description |
| Primary Opcode | 0-5 | 011111 (0x1F) |
| rD | 6-10 | Destination register |
| rA | 11-15 | Source register A |
| rB | 16-20 | Source register B |
| OE | 21 | Overflow Exception |
| XO | 22-29 | 266 (Extended opcode) |
| Rc | 30-31 | Record Condition Register |
Operation
rD ← (rA) + (rB)
The sum (rA) + (rB) is placed into rD.
Note: The add instruction performs simple addition without affecting the carry bit (XER[CA]).
Affected Registers
Condition Register (CR0 field)
(if Rc = 1)
- LT (Less Than)
- GT (Greater Than)
- EQ (Equal)
- SO (Summary Overflow)
Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).
XER (Exception Register)
(if OE = 1)
- SO (Summary Overflow)
- OV (Overflow)
For more information on condition codes see Section 2.1.3, "Condition Register," and Section 2.1.5, "XER Register," in the PowerPC Microprocessor Family: The Programming Environments manual.
Examples
Basic Addition
add r3, r1, r2 # r3 = r1 + r2 add. r3, r1, r2 # Same as above, but also sets condition register
Simple Arithmetic
# Add two values and store result lwz r4, 0(r10) # Load first value lwz r5, 4(r10) # Load second value add r6, r4, r5 # Add values
Overflow Detection
addo r3, r1, r2 # Add with overflow exception enabled # If overflow occurs, an exception is raised