Instruction Syntax

Mnemonic	Format	Flags
addze	rD,rA	OE = 0, Rc = 0
addze.	rD,rA	OE = 0, Rc = 1
addzeo	rD,rA	OE = 1, Rc = 0
addzeo.	rD,rA	OE = 1, Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rD	6-10	Destination register
rA	11-15	Source register A
Reserved	16-20	Should be zero
OE	21	Overflow Exception
XO	22-29	202 (Extended opcode)
Rc	30-31	Record Condition Register

Operation

rD ← (rA) + CA

The sum (rA) + CA is placed into rD, where CA is the carry bit from the XER register.

Note: This instruction is useful for multi-precision addition when you need to add only the carry from a previous operation.

Affected Registers

Condition Register (CR0 field)

(if Rc = 1)

• LT (Less Than)
• GT (Greater Than)
• EQ (Equal)
• SO (Summary Overflow)

Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).

XER (Exception Register)

(always)

• CA (Carry)

(if OE = 1)

• SO (Summary Overflow)
• OV (Overflow)

For more information on condition codes see Section 2.1.3, "Condition Register," and Section 2.1.5, "XER Register," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic Add to Zero Extended

addze r3, r1       # r3 = r1 + CA
addze. r3, r1      # Same as above, but also sets condition register

Multi-Precision Addition

# Add 96-bit values: (r1:r2:r3) + (r4:r5:r6) → (r7:r8:r9)
addc r9, r3, r6    # Add lowest 32 bits
adde r8, r2, r5    # Add middle 32 bits with carry
addze r7, r1       # Add highest 32 bits with carry only

Propagate Carry to Higher Word

# Continue multi-precision addition chain
addc r10, r1, r2   # First addition sets carry
adde r11, r3, r4   # Second addition uses and sets carry
addze r12, r5      # Third word only needs carry from previous

Increment with Carry

# Increment value by 1 and add any existing carry
addic r3, r1, 1    # Add 1, set carry if overflow
addze r4, r2       # Add carry to high word

Related Instructions

add, addc, adde, addme, subfze