Instruction Syntax

Mnemonic	Format	Flags
addc	rD,rA,rB	OE = 0, Rc = 0
addc.	rD,rA,rB	OE = 0, Rc = 1
addco	rD,rA,rB	OE = 1, Rc = 0
addco.	rD,rA,rB	OE = 1, Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rD	6-10	Destination register
rA	11-15	Source register A
rB	16-20	Source register B
OE	21	Overflow Exception
XO	22-29	10 (Extended opcode)
Rc	30-31	Record Condition Register

Operation

rD ← (rA) + (rB)

The sum (rA) + (rB) is placed into rD.

Note: The addc instruction sets the carry bit (XER[CA]) based on whether there was a carry out of bit 0, making it useful for starting multi-precision arithmetic sequences.

Affected Registers

Condition Register (CR0 field)

(if Rc = 1)

• LT (Less Than)
• GT (Greater Than)
• EQ (Equal)
• SO (Summary Overflow)

Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).

XER (Exception Register)

Affected: CA

Affected: SO, OV (if OE = 1)

For more information on condition codes see Section 2.1.3, "Condition Register," and Section 2.1.5, "XER Register," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic Addition with Carry

addc r3, r1, r2    # r3 = r1 + r2, set carry bit
addc. r3, r1, r2   # Same as above, but also sets condition register

Multi-Precision Addition

# Add 64-bit values in r1:r2 and r3:r4, result in r5:r6
addc r6, r2, r4    # Add low 32 bits with carry
adde r5, r1, r3    # Add high 32 bits with carry from previous addc

Overflow Detection

addco r3, r1, r2   # Add with overflow exception enabled
# If overflow occurs, an exception is raised

Related Instructions

adde, add, addi, addic, addme, addze