adde
Add Extended - 7C 00 01 14
adde
Instruction Syntax
| Mnemonic | Format | Flags |
| adde | rD,rA,rB | OE = 0, Rc = 0 |
| adde. | rD,rA,rB | OE = 0, Rc = 1 |
| addeo | rD,rA,rB | OE = 1, Rc = 0 |
| addeo. | rD,rA,rB | OE = 1, Rc = 1 |
Instruction Encoding
0
1
1
1
1
1
D
D
D
D
D
A
A
A
A
A
B
B
B
B
B
OE
0
1
0
0
0
1
0
1
0
Rc
| Field | Bits | Description |
| Primary Opcode | 0-5 | 011111 (0x1F) |
| rD | 6-10 | Destination register |
| rA | 11-15 | Source register A |
| rB | 16-20 | Source register B |
| OE | 21 | Overflow Exception |
| XO | 22-29 | 138 (Extended opcode) |
| Rc | 30-31 | Record Condition Register |
Operation
rD ← (rA) + (rB) + CA
The sum (rA) + (rB) + CA is placed into rD, where CA is the carry bit from the XER register.
Note: The adde instruction is used for multi-precision arithmetic operations, adding the carry from a previous operation.
Affected Registers
Condition Register (CR0 field)
(if Rc = 1)
- LT (Less Than)
- GT (Greater Than)
- EQ (Equal)
- SO (Summary Overflow)
Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).
XER (Exception Register)
(always)
- CA (Carry)
(if OE = 1)
- SO (Summary Overflow)
- OV (Overflow)
For more information on condition codes see Section 2.1.3, "Condition Register," and Section 2.1.5, "XER Register," in the PowerPC Microprocessor Family: The Programming Environments manual.
Examples
Basic Extended Addition
adde r3, r1, r2 # r3 = r1 + r2 + CA adde. r3, r1, r2 # Same as above, but also sets condition register
64-bit Addition (Multi-Precision)
# Add 64-bit values in r1:r2 and r3:r4, result in r5:r6 addc r6, r2, r4 # Add low 32 bits, set carry adde r5, r1, r3 # Add high 32 bits with carry from previous operation
Chain of Extended Additions
# Adding multiple 32-bit values to form larger precision addc r7, r0, r1 # Start with first addition (clear carry first) adde r8, r2, r3 # Add second pair with carry adde r9, r4, r5 # Add third pair with carry