Instruction Syntax

Mnemonic	Format	Flags
addme	rD,rA	OE = 0, Rc = 0
addme.	rD,rA	OE = 0, Rc = 1
addmeo	rD,rA	OE = 1, Rc = 0
addmeo.	rD,rA	OE = 1, Rc = 1

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	011111 (0x1F)
rD	6-10	Destination register
rA	11-15	Source register A
Reserved	16-20	Should be zero
OE	21	Overflow Exception
XO	22-29	234 (Extended opcode)
Rc	30-31	Record Condition Register

Operation

rD ← (rA) + CA + (-1)

The sum (rA) + CA + (-1) is placed into rD, where CA is the carry bit from the XER register.

Note: This instruction is useful for multi-precision subtraction and complement operations.

Affected Registers

Condition Register (CR0 field)

(if Rc = 1)

• LT (Less Than)
• GT (Greater Than)
• EQ (Equal)
• SO (Summary Overflow)

Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).

XER (Exception Register)

(always)

• CA (Carry)

(if OE = 1)

• SO (Summary Overflow)
• OV (Overflow)

For more information on condition codes see Section 2.1.3, "Condition Register," and Section 2.1.5, "XER Register," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic Add to Minus One Extended

addme r3, r1       # r3 = r1 + CA - 1
addme. r3, r1      # Same as above, but also sets condition register

Multi-Precision Subtraction

# Subtract 64-bit value (r3:r4) from (r1:r2), result in (r5:r6)
subfc r6, r4, r2   # Subtract low words with complement
addme r5, r1       # Add high word with carry and minus one

Two's Complement with Carry

# Create two's complement with existing carry
addme r3, r1       # Negate r1 and add carry from previous operation

Conditional Negation

# If carry is set, this effectively negates the value
addme r3, r1       # r3 = r1 + CA - 1
# If CA=1: r3 = r1 + 1 - 1 = r1
# If CA=0: r3 = r1 + 0 - 1 = r1 - 1

Related Instructions

add, addc, adde, addze, subf, subfme