Instruction Syntax

Mnemonic	Format	Flags
crand	crbD,crbA,crbB	-

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	010011 (0x13)
crbD	6-10	Condition Register bit Destination
crbA	11-15	Condition Register bit A
crbB	16-20	Condition Register bit B
XO	21-30	0100000010 (258)
Reserved	31	0

Operation

CR[crbD] ← CR[crbA] & CR[crbB]

The condition register AND instruction performs a logical AND operation between the specified condition register bits crbA and crbB, and stores the result in condition register bit crbD.

Note: This instruction allows complex conditional logic by combining condition register bits.

Affected Registers

Condition Register (CR)

(crbD bit only)

• CR[crbD] ← CR[crbA] & CR[crbB]

For more information on condition register operations see Section 2.1.3, "Condition Register," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic Condition Register AND

# Test multiple conditions
cmpwi cr0, r3, 0       # Compare r3 with 0 
cmpwi cr1, r4, 100     # Compare r4 with 100
crand 2, 1, 5          # CR0[GT] = CR0[GT] & CR1[GT]
# Now CR0[GT] is set only if both r3 > 0 AND r4 > 100

Complex Conditional Logic

# Create compound condition: (r3 == 0) AND (r4 != 0)
cmpwi cr0, r3, 0       # Compare r3 with 0
cmpwi cr1, r4, 0       # Compare r4 with 0
crand 2, 2, 6          # CR0[EQ] = CR0[EQ] & CR1[NE]
beq branch_if_condition # Branch if r3==0 AND r4!=0

Multi-Field Condition Testing

# Test if both values are positive
cmpwi cr0, r3, 0       # Test r3 > 0
cmpwi cr1, r4, 0       # Test r4 > 0  
crand 2, 1, 5          # CR0[EQ] = CR0[GT] & CR1[GT]
beq both_positive      # Branch if both are positive

Error Condition Combination

# Combine error flags from different sources
# Assume CR0 and CR1 contain status from different operations
crand 2, 3, 7          # Combine SO (summary overflow) bits
bso error_handler      # Branch if any overflow occurred

Related Instructions

crandc, creqv, crnand, crnor, cror, crorc, crxor